[INTERRUPT_VECTOR:PACKAGE:CORE:FUSE:LOCKBIT:PROGRAMMING:ADMIN:MEMORY:IO_MODULE:ICE_SETTINGS] 11 $000 RESET External Reset, Power-on Reset and Watchdog Reset $001 INT0 External Interrupt Request 0 $002 PCINT0 Pin Change Interrupt Request 0 $003 TIM0_CAPT Timer/Counter0 Input Capture $004 TIM0_OVF Timer/Counter0 Overflow $005 TIM0_COMPA Timer/Counter Compare Match A $006 TIM0_COMPB Timer/Counter Compare Match B $007 ANA_COMP Analog Comparator $008 WDT Watchdog Time-out $009 VLM Vcc Voltage Level Monitor $00A ADC ADC Conversion Complete [SOT] 6 [PCINT0:SPDATA:OC0A:ADC0:AIN0:PB0] [GND] [PCINT1:SPCLK:CLKI:ICP0:OC0B:ADC1:AIN1:PB1] [T0:CLKO:PCINT2:INT0:ADC2:PB2] [VCC] [RESET:PCINT3:ADC3:PB3] AVR8L_0 AVR8L [] [] [] 16 $10 27 26 29 28 31 30 [BYTE0] 3 CKOUT Output external clock 1 WDTON Watch dog timer always on 1 RSTDISBL Disable external reset 1 3 0x04 0x00 Output external clock 0x02 0x00 Watch dog timer always on 0x01 0x00 Disable external reset [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit 128 0 ATtiny5 16MHZ 1 RELEASED $1E $90 $09 AVRSimMemory8bit.SimMemory8bit 512 0 32 $40 0 NA $00 $3F NA NA $00 $3F $3F $3F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3E $3E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3D $3D $5F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3C $3C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3B $3B 0x01 0x02 0x08 $3A $3A 0x01 0x02 0x04 0x08 $39 $39 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $37 $37 0x01 0x02 $36 $36 0x01 0x02 0x04 0x08 $35 $35 0x01 0x02 $34 $34 0x01 0x02 0x04 0x40 0x80 $33 $33 0x01 0x02 0x04 0x08 0x10 0x20 $32 $32 0x80 $31 $31 0x01 0x02 0x04 0x08 0x20 0x40 0x80 $2F $2F 0x01 0x80 $2E $2E 0x01 0x02 0x10 0x20 0x40 0x80 $2D $2D 0x01 0x02 0x04 0x08 0x10 0x40 0x80 $2C $2C 0x40 0x80 $2B $2B 0x01 0x02 0x04 0x20 $2A $2A 0x01 0x02 0x04 0x20 $29 $29 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $28 $28 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $27 $27 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $26 $26 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $25 $25 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $24 $24 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $23 $23 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $22 $22 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1F $1F 0x01 0x02 0x04 0x08 0x10 0x20 0x80 $1D $1D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1C $1C 0x01 0x02 0x04 $1B $1B 0x01 0x02 $19 $19 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $17 $17 0x01 0x02 0x04 0x08 0x01 0x02 $15 $15 0x01 0x02 $14 $14 0x01 $13 $13 0x01 $12 $12 0x01 $11 $11 0x01 $10 $10 0x01 0x02 0x04 0x08 $0C $0C 0x02 $03 $03 0x01 0x02 0x04 0x08 $02 $02 0x01 0x02 0x04 0x08 $01 $01 0x01 0x02 0x04 0x08 $00 $00 0x01 0x02 0x04 0x08 16 0x4000 0x3f00 0x3f40 0x3f80 0x3fc0 0x3fc1 0x3fc2 [AD_CONVERTER:ANALOG_COMPARATOR:CPU:PORTB:EXTERNAL_INTERRUPT:TIMER_COUNTER_0:WATCHDOG] [ADMUX:ADCSRA:ADCSRB:ADCL:DIDR0] io_analo.bmp The value of these bits selects which combination of analog inputs are connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). ADMUX The ADC multiplexer Selection Register $1B $1B io_analo.bmp Y MUX1 Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). RW 0 MUX0 Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). RW 0 ADCL ADC Data Register When an ADC conversion is complete, the result is found in the ADC register. $19 $19 io_analo.bmp N ADC7 ADC Data Register Bit 7 R 0 ADC6 ADC Data Register Bit 6 R 0 ADC5 ADC Data Register Bit 5 R 0 ADC4 ADC Data Register Bit 4 R 0 ADC3 ADC Data Register Bit 3 R 0 ADC2 ADC Data Register Bit 2 R 0 ADC1 ADC Data Register Bit 1 R 0 ADC0 ADC Data Register Bit 0 R 0 ADCSRA The ADC Control and Status register A $1D $1D io_flag.bmp Y ADEN ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. RW 0 ADATE ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. RW 0 ADIF ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is requested if the ADIE bit is set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. RW 0 ADIE ADC Interrupt Enable When this bit is written to one, the ADC Conversion Complete Interrupt request is enabled. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. RW ANALIG_ADC_PRESCALER 0 ADCSRB The ADC Control and Status register B $1C $1C io_flag.bmp Y ADTS2 ADC Auto Trigger Source bit 2 If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. RW 0 ADTS1 ADC Auto Trigger Source bit 1 If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. RW 0 ADTS0 ADC Auto Trigger Source bit 0 If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. RW ANALOG_ADC_AUTO_TRIGGER_T10 0 DIDR0 Digital Input Disable Register $17 $17 io_analo.bmp Y ADC3D When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC2D When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC1D When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC0D When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 [ACSR:DIDR0] io_analo.bmp AlgComp_01 ACSR Analog Comparator Control And Status Register $1F $1F io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIC Analog Comparator Input Capture Enable When set, this bit enables the input capture function in Timer/Counter0 to be triggered by the analog comparator. In this case, the comparator output is directly connected to the input capture front-end logic, using the noise canceler and edge select features of the Timer/Counter0 input capture interrupt. To make the comparator trigger the Timer/Counter0 input capture interrupt, the ICIE1 bit in "TIMSK0 - Timer/Counter Interrupt Mask Register 0" must be set. RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW ANALOG_COMP_INTERRUPT 0 DIDR0 $17 $17 Y AIN1D AIN1 Digital Input Disable When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 AIN0D AIN0 Digital Input Disable When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 [CCP:SPH:SPL:SREG:CLKMSR:CLKPSR:OSCCAL:SMCR:PRR:VLMCSR:RSTFLR:NVMCSR:NVMCMD] [SPH:SPL] io_cpu.bmp CCP Configuration Change Protection In order to enable changing the contents of an I/O register the CCP register must first be written with the correct signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles. All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again by the CPU, and any pending interrupts will be executed according to their level and priority.When the protected I/O register signature is written, CCP[0] will read as one as long as the protected feature is enabled. CCP[7:1] will always read as zero. $3C $3C io_sph.bmp N CCP7 Configuration Change Protection bit 7 W 0 CCP6 Configuration Change Protection bit 6 W 0 CCP5 Configuration Change Protection bit 5 W 0 CCP4 Configuration Change Protection bit 4 W 0 CCP3 Configuration Change Protection bit 3 W 0 CCP2 Configuration Change Protection bit 2 W 0 CCP1 Configuration Change Protection bit 1 W 0 CCP0 Configuration Change Protection bit 0 W 0 SPH Stack Pointer High $3E $3E io_sph.bmp N SP15 Stack pointer bit 15 RW 0 SP14 Stack pointer bit 14 RW 0 SP13 Stack pointer bit 13 RW 0 SP12 Stack pointer bit 12 RW 0 SP11 Stack pointer bit 11 RW 0 SP10 Stack pointer bit 10 RW 0 SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low $3D $3D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 SREG Status Register $3F $3F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the twos complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The twos complement overflow flag V supports twos complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. RW 0 CLKMSR Clock Main Settings Register $37 $37 io_flag.bmp Y CLKMS1 Clock Main Select Bit 1 These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock. The clock system ensures glitch free switching of the main clock source. RW 0 CLKMS0 Clock Main Select Bit 0 These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock. The clock system ensures glitch free switching of the main clock source. RW 0 CLKPSR Clock Prescale Register $36 $36 io_flag.bmp Y CLKPS3 Clock Prescaler Select Bit 3 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 CLKPS2 Clock Prescaler Select Bit 2 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 CLKPS1 Clock Prescaler Select Bit 1 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 CLKPS0 Clock Prescaler Select Bit 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW CPU_CLK_PRESCALE_4_BITS_SMALL 0 OSCCAL Oscillator Calibration Value The oscillator calibration register is used to trim the calibrated internal oscillator and remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset.The application software can write this register to change the oscillator frequency. Calibration outside the range given is not guaranteed. The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the lowest frequency, and a setting of 0xFF gives the highest frequency. $39 $39 io_cpu.bmp N CAL7 Oscillator Calibration Value Bit7 RW 0 CAL6 Oscillator Calibration Value Bit6 RW 0 CAL5 Oscillator Calibration Value Bit5 RW 0 CAL4 Oscillator Calibration Value Bit4 RW 0 CAL3 Oscillator Calibration Value Bit3 RW 0 CAL2 Oscillator Calibration Value Bit2 RW 0 CAL1 Oscillator Calibration Value Bit1 RW 0 CAL0 Oscillator Calibration Value Bit0 RW 0 SMCR Sleep Mode Control Register $3A $3A io_cpu.bmp Y SM2 Sleep Mode Select Bit 2 These bits select between the available sleep modes. RW 0 SM1 Sleep Mode Select Bit 1 These bits select between the available sleep modes. RW 0 SM0 Sleep Mode Select Bit 0 These bits select between the available sleep modes. RW 0 SE Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmerpurpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. RW 0 PRR Power Reduction Register $35 $35 io_cpu.bmp Y PRADC Power Reduction ADC Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. RW 0 PRTIM0 Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. RW 0 VLMCSR Vcc Level Monitoring Control and Status Register $34 $34 io_cpu.bmp Y VLMF VLM Flag This bit is set by the VLM circuit to indicate that a voltage level condition has been triggered. The bit is cleared when the trigger level selection is set to disabled, or when voltage at VCC rises above the selected trigger level. The bit can also be cleared manually by writing a zero to it but the flag will soon be set again if the VLM condition remains. RW 0 VLMIE VLM Interrupt Enable When this bit is set the VLM interrupt is enabled. A VLM interrupt is generated every time the VLMF flag is set. RW 0 VLM2 Trigger Level of Voltage Level Monitor bit 2 This bit sets the trigger level for the voltage level monitor. RW 0 VLM1 Trigger Level of Voltage Level Monitor bit 1 This bit sets the trigger level for the voltage level monitor. RW 0 VLM0 Trigger Level of Voltage Level Monitor bit 0 This bit sets the trigger level for the voltage level monitor. RW 0 RSTFLR Reset Flag Register $3B $3B io_cpu.bmp Y WDRF Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. RW 0 EXTRF External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. RW 0 PORF Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. RW 0 NVMCSR Non-Volatile Memory Control and Status Register $32 $32 io_cpu.bmp Y NVMBSY Non-Volatile Memory Busy This bit indicates the NVM Memory (Flash memory and Lock Bits) is busy, being programmed. This bit is set when a program operation is started, and it remains set until the operation has been completed. RW 0 NVMCMD Non-Volatile Memory Command $33 $33 io_cpu.bmp N NVMCMD5 RW 0 NVMCMD4 RW 0 NVMCMD3 RW 0 NVMCMD2 RW 0 NVMCMD1 RW 0 NVMCMD0 RW 0 [PORTCR:PUEB:PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTCR Port Control Register $0C $0C io_flag.bmp Y BBMB Break-Before-Make Mode Enable RW 0 PUEB Pull-up Enable Control Register $03 $03 io_flag.bmp N PUEB3 RW 0 PUEB2 RW 0 PUEB1 RW 0 PUEB0 RW 0 DDRB Data Direction Register, Port B $01 $01 io_flag.bmp N DDB3 RW 0 DDB2 RW 0 DDB1 RW 0 DDB0 RW 0 PINB Port B Data register $00 $00 io_port.bmp N PINB3 RW 0 PINB2 RW 0 PINB1 RW 0 PINB0 RW 0 PORTB Input Pins, Port B $02 $02 io_port.bmp N PORTB3 RW 0 PORTB2 RW 0 PORTB1 RW 0 PORTB0 RW 0 [EICRA:EIMSK:EIFR:PCICR:PCIFR:PCMSK] io_ext.bmp EICRA External Interrupt Control Register A $15 $15 io_flag.bmp Y ISC01 Interrupt Sense Control 0 Bit 1 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC00 Interrupt Sense Control 0 Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 EIMSK External Interrupt Mask register $13 $13 io_flag.bmp Y INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. RW 0 EIFR External Interrupt Flag register $14 $14 io_flag.bmp Y INTF0 External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. RW 0 PCICR Pin Change Interrupt Control Register $12 $12 io_flag.bmp Y PCIE0 Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT3..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT3..0 pins are enabled individually by the PCMSK Register. RW 0 PCIFR Pin Change Interrupt Flag Register $11 $11 io_flag.bmp Y PCIF0 Pin Change Interrupt Flag 0 When a logic change on any PCINT3..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCMSK Pin Change Mask Register $10 $10 io_flag.bmp Y PCINT3 Pin Change Enable Mask 3 Each PCINT3..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. RW 0 PCINT2 Pin Change Enable Mask 2 Each PCINT3..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. RW 0 PCINT1 Pin Change Enable Mask 1 Each PCINT3..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. RW 0 PCINT0 Pin Change Enable Mask 0 Each PCINT3..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. RW 0 [TCCR0A:TCCR0B:TCCR0C:TCNT0H:TCNT0L:OCR0AH:OCR0AL:OCR0BH:OCR0BL:ICR0H:ICR0L:TIMSK0:TIFR0:GTCCR] [TCNT0H:TCNT0L];[OCR0AH:OCR0AL];[OCR0BH:OCR0BL];[ICR0H:ICR0L] io_timer.bmp TCCR0A Timer/Counter 0 Control Register A $2E $2E io_flag.bmp Y COM0A1 Compare Output Mode for Channel A bit 1 The COM0A1:0 and COM0B1:0 control the behaviour of Output Compare pins OC0A and OC0B, respectively. If one or both COM0A1:0 bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. Similarly, if one or both COM0B1:0 bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver. RW 0 COM0A0 Compare Output Mode for Channel A bit 0 The COM0A1:0 and COM0B1:0 control the behaviour of Output Compare pins OC0A and OC0B, respectively. If one or both COM0A1:0 bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. Similarly, if one or both COM0B1:0 bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver. RW 0 COM0B1 Compare Output Mode for Channel B bit 1 The COM0A1:0 and COM0B1:0 control the behaviour of Output Compare pins OC0A and OC0B, respectively. If one or both COM0A1:0 bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. Similarly, if one or both COM0B1:0 bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver. W 0 COM0B0 Compare Output Mode for Channel B bit 0 The COM0A1:0 and COM0B1:0 control the behaviour of Output Compare pins OC0A and OC0B, respectively. If one or both COM0A1:0 bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. Similarly, if one or both COM0B1:0 bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output drive RW 0 WGM01 Waveform Generation Mode Combined with WGM03:2 bits of TCCR0B, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform to generate. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation(PWM) modes. RW 0 WGM00 Waveform Generation Mode Combined with WGM03:2 bits of TCCR0B, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform to generate. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation(PWM) modes. RW 0 TCCR0B Timer/Counter 0 Control Register B $2D $2D io_flag.bmp Y ICNC0 Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP0) is filtered. The filter function requires four successive equal valued samples of the ICP0 pin for changing its output. The Input Capture istherefore delayed by four Oscillator cycles when the noise canceler is enabled. RW 0 ICES0 Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP0) that is used to trigger a capture event. When the ICES0 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES0 bit is written to one, a rising (positive) edge will trigger the capture.When a capture is triggered according to the ICES0 setting, the counter value is copied into the Input Capture Register (ICR0). The event will also set the Input Capture Flag (ICF0), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR0 is used as TOP value (see description of the WGM03:0 bits located in theTCCR0A and the TCCR0B Register), the ICP0 is disconnected and consequently the Input Capture function is disabled. RW 0 WGM03 Waveform Generation Mode Combined with WGM01:0 bits of TCCR0B, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform to generate. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation(PWM) modes. RW 0 WGM02 Waveform Generation Mode Combined with WGM01:0 bits of TCCR0B, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform to generate. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation(PWM) modes. RW 0 CS02 Clock Select The three Clock Select bits set the clock source to be used by the Timer/Counter. RW 0 CS01 Clock Select The three Clock Select bits set the clock source to be used by the Timer/Counter RW 0 CS00 Clock Select The three Clock Select bits set the clock source to be used by the Timer/Counter RW CLK_SEL_3BIT_EXT 0 TCCR0C Timer/Counter 0 Control Register C $2C $2C io_flag.bmp Y FOC0A Force Output Compare for Channel A The FOC0A/FOC0B bits are only active when the WGM03:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR0A is written when operating in a PWM mode. When writing a logical one to the FOC0A/FOC0B bit, an immediate compare match is forced on the Waveform Generation unit.The OC0A/OC0B output is changed according to its COM0x1:0 bits setting. Note that the FOC0A/FOC0B bits are implemented as strobes. Therefore it is the value present in the COM0x1:0 bits that determine the effect of the forced compare. A FOC0A/FOC0B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR0A as TOP. The FOC0A/FOC0B bits are always read as zero. W 0 FOC0B Force Output Compare for Channel B The FOC0A/FOC0B bits are only active when the WGM03:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR0A is written when operating in a PWM mode. When writing a logical one to the FOC0A/FOC0B bit, an immediate compare match is forced on the Waveform Generation unit.The OC0A/OC0B output is changed according to its COM0x1:0 bits setting. Note that the FOC0A/FOC0B bits are implemented as strobes. Therefore it is the value present in the COM0x1:0 bits that determine the effect of the forced compare. A FOC0A/FOC0B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR0A as TOP. The FOC0A/FOC0B bits are always read as zero. W 0 TCNT0H Timer/Counter0 High The two Timer/Counter I/O locations (TCNT0H and TCNT0L, combined TCNT0) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. Modifying the counter (TCNT0) while the counter is running introduces a risk of missing a compare match between TCNT0 and one of the OCR0x Registers. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock for all compare. $29 $29 io_timer.bmp N TCNT0_15 RW 0 TCNT0_14 RW 0 TCNT0_13 RW 0 TCNT0_12 RW 0 TCNT0_11 RW 0 TCNT0_10 RW 0 TCNT0_9 RW 0 TCNT0_8 RW 0 TCNT0L Timer/Counter0 Low The two Timer/Counter I/O locations (TCNT0H and TCNT0L, combined TCNT0) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. Modifying the counter (TCNT0) while the counter is running introduces a risk of missing a compare match between TCNT0 and one of the OCR0x Registers. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock for all compare. $28 $28 io_timer.bmp N TCNT0_7 RW 0 TCNT0_6 RW 0 TCNT0_5 RW 0 TCNT0_4 RW 0 TCNT0_3 RW 0 TCNT0_2 RW 0 TCNT0_1 RW 0 TCNT0_0 RW 0 OCR0AH Timer/Counter 0 Output Compare Register A High The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. $27 $27 io_timer.bmp N OCR0A15 RW 0 OCR0A14 RW 0 OCR0A13 RW 0 OCR0A12 RW 0 OCR0A11 RW 0 OCR0A10 RW 0 OCR0A9 RW 0 OCR0A8 RW 0 OCR0AL Timer/Counter 0 Output Compare Register A Low The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. $26 $26 io_timer.bmp N OCR0A7 RW 0 OCR0A6 RW 0 OCR0A5 RW 0 OCR0A4 RW 0 OCR0A3 RW 0 OCR0A2 RW 0 OCR0A1 RW 0 OCR0A0 RW 0 OCR0BH Timer/Counter0 Output Compare Register B High The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. $25 $25 io_timer.bmp N OCR0B15 RW 0 OCR0B14 RW 0 OCR0B13 RW 0 OCR0B12 RW 0 OCR0B11 RW 0 OCR0B10 RW 0 OCR0B9 RW 0 OCR0B8 RW 0 OCR0BL Timer/Counter0 Output Compare Register B Low The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. $24 $24 io_timer.bmp N OCR0B7 RW 0 OCR0B6 RW 0 OCR0B5 RW 0 OCR0B4 RW 0 OCR0B3 RW 0 OCR0B2 RW 0 OCR0B1 RW 0 OCR0B0 RW 0 ICR0H Input Capture Register High Byte The Input Capture is updated with the counter (TCNT0) value each time an event occurs on the ICP0 pin (or optionally on the Analog Comparator output for Timer/Counter0). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. $23 $23 io_timer.bmp N ICR0_15 RW 0 ICR0_14 RW 0 ICR0_13 RW 0 ICR0_12 RW 0 ICR0_11 RW 0 ICR0_10 RW 0 ICR0_9 RW 0 ICR0_8 RW 0 ICR0L Input Capture Register Low Byte The Input Capture is updated with the counter (TCNT0) value each time an event occurs on the ICP0 pin (or optionally on the Analog Comparator output for Timer/Counter0). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. $22 $22 io_timer.bmp N ICR0_7 RW 0 ICR0_6 RW 0 ICR0_5 RW 0 ICR0_4 RW 0 ICR0_3 RW 0 ICR0_2 RW 0 ICR0_1 RW 0 ICR0_0 RW 0 TIMSK0 Timer Interrupt Mask Register 0 $2B $2B io_flag.bmp Y ICIE0 Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICF0 Flag, located in TIFR0, is set. RW 0 OCIE0B Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF0B flag, located in TIFR0, is set. RW 0 OCIE0A Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF0A flag, located in TIFR0, is set. RW 0 TOIE0 Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV0 flag, located in TIFR0, is set. RW 0 TIFR0 Overflow Interrupt Enable $2A $2A io_flag.bmp Y ICF0 Input Capture Flag This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register (ICR0) is set by the WGM03:0 to be used as the TOP value, the ICF0 flag is set when the counter reaches the TOP value. ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF0 can be cleared by writing a logic one to its bit location. RW 0 OCF0B Timer Output Compare Flag 0B This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output Compare Register B (OCR0B). Note that a Forced Output Compare (0B) strobe will not set the OCF0B flag.OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. RW 0 OCF0A Timer Output Compare Flag 0A This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output Compare Register A (OCR0A). Note that a Forced Output Compare (1A) strobe will not set the OCF0A flag. OCF0A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF0A can be cleared by writing a logic one to its bit location. RW 0 TOV0 Timer Overflow Flag The setting of this flag is dependent of the WGM03:0 bits setting. In Normal and CTC modes, the TOV0 flag is set when the timer overflows. TOV0 is automatically cleared when the Timer/Counter0 Overflow Interrupt Vector is executed. Alternatively, TOV0 can be cleared by writing a logic one to its bit location. RW 0 GTCCR General Timer/Counter Control Register $2F $2F io_flag.bmp Y TSM Timer Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR bit is kept, hence keeping the Prescaler Reset signal asserted.This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting. RW 0 PSR Prescaler Reset When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. RW 0 [WDTCSR] io_watch.bmp WDTCSRWatchdog Timer Control and Status Register$31$31 d io_flag.bmpYWDIFWatchdog Timer Interrupt FlagThis bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDTIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDTIF is cleared by writing a logic one to the flag. When the WDTIE is set, the Watchdog Time-out Interrupt is requested.RW0WDIEWatchdog Timer Interrupt EnableWhen this bit is written to one, the Watchdog interrupt request is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is requested if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDTIF. Executing the corresponding interrupt vector will clear WDTIE and WDTIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDTIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be appliedRW0WDP3Watchdog Timer Prescaler Bit 3The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.RW0WDEWatch Dog EnableWDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.RW0WDP2Watch Dog Timer Prescaler bit 2The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.WDOG_TIMER_PRESCALE_4BITSRW0WDP1Watch Dog Timer Prescaler bit 1The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.RW0WDP0Watch Dog Timer Prescaler bit 0The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.RW0 [STK600:SIMULATOR2:AVRISPmkII] libATtiny10.dll