[CORE:LOCKBIT:FUSE:INTERRUPT_VECTOR:PROGRAMMING:MEMORY:ADMIN:PACKAGE:IO_MODULE:ICE_SETTINGS]AVR8L_0AVR8L[][][]16$10272629283130[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled320x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabledLB1LockbitLB2Lockbit[BYTE0]6BODLEVEL2Brown-out Detector trigger level1BODLEVEL1Brown-out Detector trigger level1BODLEVEL0Brown-out Detector trigger level1CKOUTOutput external clock1CKOUTOutput external clock1WDTONWatch dog timer always on1RSTDISBLDisable external reset170x700x07Brown-out detection disabled; [BODLEVEL=111]0x700x06Brown-out detection level at VCC=1.8 V; [BODLEVEL=110]0x700x05Brown-out detection level at VCC=2.7 V; [BODLEVEL=101]0x700x04Brown-out detection level at VCC=4.3 V; [BODLEVEL=100]0x040x00Output external clock0x020x00Watch dog timer always on0x010x00Disable external reset17$000RESETExternal Reset, Power-on Reset and Watchdog Reset$001INT0External Interrupt Request 0$002PCINT0Pin Change Interrupt Request 0$003PCINT1Pin Change Interrupt Request 1$004WDTWatchdog Time-out$005TIM1_CAPTTimer/Counter1 Input Capture$006TIM1_COMPA Timer/Counter1 Compare Match A$007TIM1_COMPB Timer/Counter1 Compare Match B$008TIM1_OVFTimer/Counter1 Overflow$009TIM0_COMPATimer/Counter0 Compare Match A$00ATIM0_COMPBTimer/Counter0 Compare Match B$00BTIM0_OVFTimer/Counter0 Overflow$00CANA_COMPAnalog Comparator$00DADC ADCConversion Complete$00ETWI_SLAVETwo-Wire Interface$00FSPISerial Peripheral Interface$010QTRIPTouch Sensing1280AVRSimMemory8bit.SimMemory8bit20480256$400NA$00$3FNANA$00$3F$3F$3F0x010x020x040x080x100x200x400x80$3E$3E0x010x020x040x080x100x200x400x80$3D$3D$5F0x010x020x040x080x100x200x400x80$3C$3C0x010x020x040x080x100x200x400x80$3B$3B0x010x020x08$3A$3A0x010x020x040x080x100x400x80$39$390x010x020x040x080x100x200x400x80$38$38$37$370x010x02$36$360x010x020x040x08$35$350x010x020x040x080x10$34$34$33$330x010x020x040x080x100x20$32$320x80$31$310x010x020x040x080x200x400x80$30$30$2F$2F$2E$2E$2D$2D0x010x020x040x080x100x200x80$2C$2C0x010x020x04$2B$2B0x010x020x040x080x100x200x400x80$2A$2A0x010x020x040x080x100x200x400x80$29$290x010x020x040x080x100x200x400x80$28$280x010x020x040x080x100x200x400x80$27$270x010x020x040x080x100x200x400x80$26$260x010x020x040x080x100x200x80$25$250x010x020x040x080x100x200x80$24$240x010x020x040x080x100x200x400x80$23$230x010x020x040x080x100x200x400x80$22$220x010x020x040x080x100x200x400x80$21$210x010x020x040x080x100x200x400x80$20$200x010x020x040x080x100x200x400x80$1F$1F0x010x020x040x080x100x200x400x80$1E$1E0x010x020x040x080x100x20$1D$1D0x010x020x040x080x100x20$1C$1C0x010x020x040x080x100x20$1B$1B0x010x020x040x080x100x20$1A$1A0x010x020x040x080x100x20$19$190x010x020x100x200x400x80$18$180x010x020x040x080x100x200x400x80$17$170x010x020x040x080x100x200x400x80$16$160x010x020x040x080x100x200x400x80$15$150x010x020x040x080x100x200x400x80$14$140x010x020x040x080x100x200x400x80$13$130x040x400x80$12$120x010x020x040x080x100x200x400x80$11$110x010x020x040x08$10$100x010x020x040x080x40$0F$0F0x010x020x040x080x100x200x400x80$0E$0E0x010x020x040x080x100x200x400x80$0D$0D0x010x020x040x080x100x200x400x80$0C$0C0x010x100x200x40$0B$0B0x010x100x200x40$0A$0A0x010x020x040x08$09$090x010x020x040x080x100x200x400x80$08$080x010x020x040x100x200x400x80$07$070x010x020x040x08$06$060x010x020x040x08$05$050x010x020x040x08$04$040x010x020x040x08$03$030x010x020x040x080x100x200x400x80$02$020x010x020x040x080x100x200x400x80$01$010x010x020x040x080x100x200x400x80$00$000x010x020x040x080x100x200x400x80320x40000x3f000x3f400x3f800x3fc00x3fc10x3fc2ATtiny4012MHZ1RELEASED$1E$92$0E[SOIC:VQFN]14[PCINT8:ADC8][PCINT7:ADC7][(PCINT6:ADC6][PCINT5:ADC5:OC0B][PCINT4:ADC4:T0][PCINT3:ADC3][PCINT2:ADC2:AIN1][(PCINT1:ADC1:AIN0][PCINT0:ADC0][GND][VCC][CLKI:PCINT17)][MOSI:SDA:PCINT16][RESET:PCINT15][INT0:CLKO:MISO:PCINT14][SCK:SCL:ICP1:T1:PCINT13][OC0A:SS:PCINT12][ADC11:PCINT11][ADC10:PCINT10)][ADC9:PCINT9]20[PCINT6:ADC6][PCINT5:ADC5:OC0B][PCINT4:ADC4:T0][(PCINT3:ADC3][(PCINT2:ADC2:AIN1][PCINT1:ADC1:AIN0][PCINT0:ADC0][GND][VCC][PCINT17:CLKI][(MOSI:SDA:PCINT16][RESET:PCINT15][(INT0:CLKO:MISO:PCINT14][(SCK:SCL:ICP1:T1:PCINT13][OC0A:SS:PCINT12][ADC11:PCINT11][ADC10:PCINT10][ADC9/PCINT9][ADC8:PCINT8][ADC7:PCINT7][WATCHDOG:AD_CONVERTER:ANALOG_COMPARATOR:TWI:CPU:EXTERNAL_INTERRUPT:PORTB:PORTC:TIMER_COUNTER_0:PORTA][WDTCSR]io_watch.bmpWDTCSRWatchdog Timer Control and Status Register$31$31
d
io_flag.bmpYWDIFWatchdog Timer Interrupt FlagThis bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDTIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDTIF is cleared by writing a logic one to the flag. When the WDTIE is set, the Watchdog Time-out Interrupt is requested.RW0WDIEWatchdog Timer Interrupt EnableWhen this bit is written to one, the Watchdog interrupt request is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is requested if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDTIF. Executing the corresponding interrupt vector will clear WDTIE and WDTIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDTIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be appliedRW0WDP3Watchdog Timer Prescaler Bit 3The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.RW0WDEWatch Dog EnableWDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.RW0WDP2Watch Dog Timer Prescaler bit 2The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.WDOG_TIMER_PRESCALE_4BITSRW0WDP1Watch Dog Timer Prescaler bit 1The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.RW0WDP0Watch Dog Timer Prescaler bit 0The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.RW0[ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0]((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);io_analo.bmpAD Converter Feature list: 10-bit Resolution, 1 LSB Integral Non-linearity, ± 2 LSB Absolute Accuracy, 13μs Conversion Time, 15 kSPS at Maximum Resolution, Eight Multiplexed Single Ended Input Channels, Temperature Sensor Input Channel, Optional Left Adjustment for ADC Result Readout, 0 - VCC ADC Input Voltage Range, 1.1V ADC Reference Voltage, Free Running or Single Conversion Mode, ADC Start Conversion by Auto Triggering on Interrupt Sources, Interrupt on ADC Conversion Complete, Sleep Mode Noise CancelerADMUXThe ADC multiplexer Selection RegisterThese bits select the voltage reference for the ADC, as shown in Table 15-3. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.$10$10io_analo.bmpYREFSReference Selection BitIf this bit is changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). Also note, that when these bits are changed, the next conversion will take 25 ADC clock cycles.RW0MUX3Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADCSRAThe ADC Control and Status register$12$12io_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effectRW0ADATEADC Auto Trigger EnableWhen this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RWANALIG_ADC_PRESCALER0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right $0F$0Fio_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right$0E$0Eio_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0ADCSRBADC Control and Status Register B$11$11io_analo.bmpYADLARADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions.R0ADTS2ADC Auto Trigger Source 2If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW0ADTS1ADC Auto Trigger Source 1If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW0ADTS0ADC Auto Trigger Source 0If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RWANALIG_ADC_AUTO_TRIGGER30DIDR0Digital Input Disable Register 0$0D$0Dio_analo.bmpYADC7DADC6 Digital input DisableWhen a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input bufferRW0ADC6DADC5 Digital input DisableWhen a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input bufferRW0ADC5DADC4 Digital input DisableWhen a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input bufferRW0ADC4DADC3 Digital input DisableWhen a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input bufferRW0ADC3DAREF Digital Input DisableWhen a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input bufferRW0ADC2DADC2 Digital input DisableWhen a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input bufferRW0ADC1DADC1 Digital input DisableWhen a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input bufferRW0ADC0DADC0 Digital input DisableWhen a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input bufferRW0[ACSRA:ACSRB]io_analo.bmpAlgComp_01ACSRBAnalog Comparator Control And Status Register B$13$13io_analo.bmpYHSELHysteresis SelectRW0HLEVHysteresis LevelRW0ACMEAnalog Comparator Multiplexer EnableRW0ACSRAAnalog Comparator Control And Status Register A$14$14io_analo.bmpYACDAnalog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACBGAnalog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.RW0ACOAnalog Compare OutputThe output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.RNAACIAnalog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.RW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.RW0ACICAnalog Comparator Input Capture EnableWhen written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is then directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-rupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set.RW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RWANALOG_COMP_INTERRUPT0[TWSCRA:TWSCRB:TWSSRA:TWSA:TWSD:TWSAM]io_com.bmpTWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI TWSCRATWI Slave Control Register A$2D$2Dio_com.bmpYTWSHETWI SDA Hold Time EnableRW0TWDIETWI Data Interrupt EnableRW0TWASIETWI Address/Stop Interrupt EnableRW0TWENTwo-Wire Interface EnableRW0TWSIETWI Stop Interrupt EnableRW0TWPMETWI Promiscuous Mode EnableRWCOMM_TW_BUS_TIMEOUT0TWSMETWI Smart Mode EnableRW0TWSCRBTWI Slave Control Register B$2C$2Cio_com.bmpYTWAATWI Acknowledge ActionThis bit defines the slave's acknowledge behavior after an address or data byte has been received from the master. Depending on the TWSME bit in TWSCRA the Acknowledge Action is executed either when a valid command has been written to TWCMDn bits, or when the data register has been read.RW0TWCMD1Writing these bits triggers the slave operation as defined by Table 17-2. The type of operation depends on the TWI slave interrupt flags, TWDIF and TWASIF. The Acknowledge Action is only executed when the slave receives data bytes or address byte from the master.RW0TWCMD0Writing these bits triggers the slave operation as defined by Table 17-2. The type of operation depends on the TWI slave interrupt flags, TWDIF and TWASIF. The Acknowledge Action is only executed when the slave receives data bytes or address byte from the master.RW0TWSSRATWI Slave Status Register A$2B$2Bio_com.bmpNTWDIFTWI Data Interrupt Flag.This flag is set when a data byte has been successfully received, i.e. no bus errors or collisions have occurred during the operation. When this flag is set the slave forces the SCL line low, stretching the TWI clock period. The SCL line is released by clearing the interrupt flags. Writing a one to this bit will clear the flag. This flag is also automatically cleared when writing a valid command to the TWCMDn bits in TWSCRB.RW0TWASIFTWI Address/Stop Interrupt FlagThis flag is set when the slave detects that a valid address has been received, or when a transmit collision has been detected. When this flag is set the slave forces the SCL line low, stretching the TWI clock period. The SCL line is released by clearing the interrupt flags. If TWASIE in TWSCRA is set a STOP condition on the bus will also set TWASIF.Writing a one to this bit will clear the flag. This flag is also automatically cleared when writing a valid command to the TWCMDn bits in TWSCRB.RW0TWCHTWI Clock HoldThis bit is set when the slave is holding the SCL line low. This bit is read-only, and set when TWDIF or TWASIF is set. The bit can be cleared indirectly by clearing the interrupt flags and releasing the SCL line.RW0TWRATWI Receive AcknowledgeThis bit contains the most recently received acknowledge bit from the master. This bit is read-only. When zero, the most recent acknowledge bit from the maser was ACK and, when one, the most recent acknowledge bit was NACK.RW0TWCTWI CollisionThis bit is set when the slave was not able to transfer a high data bit or a NACK bit. When a collision is detected, the slave will commence its normal operation, and disable data and acknowledge output. No low values are shifted out onto the SDA line.This bit is cleared by writing a one to it. The bit is also cleared automatically when a START or Repeated START condition is detected.RW0TWBETWI Bus ErrorThis bit is set when an illegal bus condition has occured during a transfer. An illegal bus condition occurs if a Repeated START or STOP condition is detected, and the number of bits from the previous START condition is not a multiple of nine.This bit is cleared by writing a one to it.RW0TWDIRTWI Read/Write DirectionThis bit indicates the direction bit from the last address packet received from a master. When this bit is one, a master read operation is in progress. When the bit is zero a master write operation is in progress.RW0TWASTWI Address or StopThis bit indicates why the TWASIF bit was last set. If zero, a stop condition caused TWASIF to be set. If one, address detection caused TWASIF to be set.RW0TWSATWI Slave Address RegisterThe slave address register contains the TWI slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA[0]) is used for general call address recognition. Setting TWSA[0] enables general call address recognition logic.When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 ot the slave address. The next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is not used in this mode.$2A$2Aio_flag.bmpYTWSA7TWI slave address bitThe slave address register contains the TWI slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA[0]) is used for general call address recognition. Setting TWSA[0] enables general call address recognition logic.When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 ot the slave address. The next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is not used in this mode.RW0TWSA6TWI slave address bitThe slave address register contains the TWI slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA[0]) is used for general call address recognition. Setting TWSA[0] enables general call address recognition logic.When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 ot the slave address. The next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is not used in this mode.RW0TWSA5TWI slave address bitThe slave address register contains the TWI slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA[0]) is used for general call address recognition. Setting TWSA[0] enables general call address recognition logic.When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 ot the slave address. The next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is not used in this mode.RW0TWSA4TWI slave address bitThe slave address register contains the TWI slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA[0]) is used for general call address recognition. Setting TWSA[0] enables general call address recognition logic.When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 ot the slave address. The next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is not used in this mode.RW0TWSA3TWI slave address bitThe slave address register contains the TWI slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA[0]) is used for general call address recognition. Setting TWSA[0] enables general call address recognition logic.When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 ot the slave address. The next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is not used in this mode.RW0TWSA2TWI slave address bitThe slave address register contains the TWI slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA[0]) is used for general call address recognition. Setting TWSA[0] enables general call address recognition logic.When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 ot the slave address. The next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is not used in this mode.RW0TWSA1TWI slave address bitThe slave address register contains the TWI slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA[0]) is used for general call address recognition. Setting TWSA[0] enables general call address recognition logic.When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 ot the slave address. The next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is not used in this mode.RW0TWSA0TWI slave address bitThe slave address register contains the TWI slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA[0]) is used for general call address recognition. Setting TWSA[0] enables general call address recognition logic.When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 ot the slave address. The next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR flag is updated. If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is not used in this mode.RW0TWSDTWI Slave Data Register$28$28io_flag.bmpYTWSD7TWI slave data bitThe data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set. When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte transfer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the acknowledge bit from the master. The TWDIF and the TWCH bits are then set. When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in the data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the TWAA bit in TWSCRB. Accessing TWSD will clear the slave interrupt flags and the TWCH bit.RW0TWSD6TWI slave data bitThe data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set. When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte transfer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the acknowledge bit from the master. The TWDIF and the TWCH bits are then set. When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in the data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the TWAA bit in TWSCRB. Accessing TWSD will clear the slave interrupt flags and the TWCH bit.RW0TWSD5TWI slave data bitThe data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set. When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte transfer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the acknowledge bit from the master. The TWDIF and the TWCH bits are then set. When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in the data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the TWAA bit in TWSCRB. Accessing TWSD will clear the slave interrupt flags and the TWCH bit.RW0TWSD4TWI slave data bitThe data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set. When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte transfer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the acknowledge bit from the master. The TWDIF and the TWCH bits are then set. When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in the data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the TWAA bit in TWSCRB. Accessing TWSD will clear the slave interrupt flags and the TWCH bit.RW0TWSD3TWI slave data bitThe data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set. When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte transfer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the acknowledge bit from the master. The TWDIF and the TWCH bits are then set. When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in the data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the TWAA bit in TWSCRB. Accessing TWSD will clear the slave interrupt flags and the TWCH bit.RW0TWSD2TWI slave data bitThe data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set. When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte transfer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the acknowledge bit from the master. The TWDIF and the TWCH bits are then set. When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in the data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the TWAA bit in TWSCRB. Accessing TWSD will clear the slave interrupt flags and the TWCH bit.RW0TWSD1TWI slave data bitThe data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set. When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte transfer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the acknowledge bit from the master. The TWDIF and the TWCH bits are then set. When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in the data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the TWAA bit in TWSCRB. Accessing TWSD will clear the slave interrupt flags and the TWCH bit.RW0TWSD0TWI slave data bitThe data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set. When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte transfer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the acknowledge bit from the master. The TWDIF and the TWCH bits are then set. When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in the data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the TWAA bit in TWSCRB. Accessing TWSD will clear the slave interrupt flags and the TWCH bit.RW0TWSAMTWI Slave Address Mask Register$29$29io_com.bmpNTWSAM7TWI Address Mask Bit 7These bits can act as a second address match register, or an address mask register, depending on the TWAE setting. If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in TWSAM can mask (disable) the corresponding address bit in the TWSA register. If the mask bit is one the address match between the incoming address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match. If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to the TWSA register. In this mode, the slave will match on 2 unique addresses, one in TWSA and the other in TWSAM.RW1TWSAM6TWI Address Mask Bit 6These bits can act as a second address match register, or an address mask register, depending on the TWAE setting. If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in TWSAM can mask (disable) the corresponding address bit in the TWSA register. If the mask bit is one the address match between the incoming address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match. If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to the TWSA register. In this mode, the slave will match on 2 unique addresses, one in TWSA and the other in TWSAM.RW1TWSAM5TWI Address Mask Bit 5These bits can act as a second address match register, or an address mask register, depending on the TWAE setting. If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in TWSAM can mask (disable) the corresponding address bit in the TWSA register. If the mask bit is one the address match between the incoming address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match. If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to the TWSA register. In this mode, the slave will match on 2 unique addresses, one in TWSA and the other in TWSAM.RW1TWSAM4TWI Address Mask Bit 4These bits can act as a second address match register, or an address mask register, depending on the TWAE setting. If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in TWSAM can mask (disable) the corresponding address bit in the TWSA register. If the mask bit is one the address match between the incoming address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match. If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to the TWSA register. In this mode, the slave will match on 2 unique addresses, one in TWSA and the other in TWSAM.RW1TWSAM3TWI Address Mask Bit 3These bits can act as a second address match register, or an address mask register, depending on the TWAE setting. If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in TWSAM can mask (disable) the corresponding address bit in the TWSA register. If the mask bit is one the address match between the incoming address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match. If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to the TWSA register. In this mode, the slave will match on 2 unique addresses, one in TWSA and the other in TWSAM.RW1TWSAM2TWI Address Mask Bit 2These bits can act as a second address match register, or an address mask register, depending on the TWAE setting. If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in TWSAM can mask (disable) the corresponding address bit in the TWSA register. If the mask bit is one the address match between the incoming address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match. If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to the TWSA register. In this mode, the slave will match on 2 unique addresses, one in TWSA and the other in TWSAM.RW1TWSAM1TWI Address Mask Bit 1These bits can act as a second address match register, or an address mask register, depending on the TWAE setting. If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in TWSAM can mask (disable) the corresponding address bit in the TWSA register. If the mask bit is one the address match between the incoming address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match. If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to the TWSA register. In this mode, the slave will match on 2 unique addresses, one in TWSA and the other in TWSAM.RW1TWAETWI Address EnableBy default, this bit is zero and the TWSAM bits acts as an address mask to the TWSA register. If this bit is set to one, the slave address match logic responds to the two unique addresses in TWSA and TWSAMRW1[CCP:SPH:SPL:SREG:CLKMSR:CLKPSR:OSCCAL:PRR:RSTFLR:NVMCSR:NVMCMD:MCUCR:GIMSK:GIFR:RAMAR:RAMDR]
[SPH:SPL]
io_cpu.bmpCCPConfiguration Change ProtectionIn order to enable changing the contents of an I/O register the CCP register must first be written with the correct signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles. All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again by the CPU, and any pending interrupts will be executed according to their level and priority.When the protected I/O register signature is written, CCP[0] will read as one as long as the protected feature is enabled. CCP[7:1] will always read as zero.$3C$3Cio_sph.bmpNCCP7Configuration Change Protection bit 7W0CCP6Configuration Change Protection bit 6W0CCP5Configuration Change Protection bit 5W0CCP4Configuration Change Protection bit 4W0CCP3Configuration Change Protection bit 3W0CCP2Configuration Change Protection bit 2W0CCP1Configuration Change Protection bit 1W0CCP0Configuration Change Protection bit 0W0SPHStack Pointer High$3E$3Eio_sph.bmpNSP15Stack pointer bit 15RW0SP14Stack pointer bit 14RW0SP13Stack pointer bit 13RW0SP12Stack pointer bit 12RW0SP11Stack pointer bit 11RW0SP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW0SPLStack Pointer Low$3D$3Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0SREGStatus Register$3F$3Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the twos complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe twos complement overflow flag V supports twos complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information.RW0CLKMSRClock Main Settings Register$37$37io_flag.bmpYCLKMS1Clock Main Select Bit 1These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock. The clock system ensures glitch free switching of the main clock source.RW0CLKMS0Clock Main Select Bit 0These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock. The clock system ensures glitch free switching of the main clock source.RW0CLKPSRClock Prescale Register$36$36io_flag.bmpYCLKPS3Clock Prescaler Select Bit 3These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0CLKPS2Clock Prescaler Select Bit 2These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0CLKPS1Clock Prescaler Select Bit 1These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0CLKPS0Clock Prescaler Select Bit 0These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RWCPU_CLK_PRESCALE_4_BITS_SMALL0OSCCALOscillator Calibration ValueThe oscillator calibration register is used to trim the calibrated internal oscillator and remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset.The application software can write this register to change the oscillator frequency. Calibration outside the range given is not guaranteed. The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the lowest frequency, and a setting of 0xFF gives the highest frequency.$39$39io_cpu.bmpNCAL7Oscillator Calibration Value Bit7RW0CAL6Oscillator Calibration Value Bit6RW0CAL5Oscillator Calibration Value Bit5RW0CAL4Oscillator Calibration Value Bit4RW0CAL3Oscillator Calibration Value Bit3RW0CAL2Oscillator Calibration Value Bit2RW0CAL1Oscillator Calibration Value Bit1RW0CAL0Oscillator Calibration Value Bit0RW0PRRPower Reduction Register$35$35io_cpu.bmpYPRTWIPower Reduction TWIRW0PRSPIPower Reduction Serial Peripheral InterfaceRW0PRTIM1Power Reduction Timer/Counter1Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.RW0PRTIM0Power Reduction Timer/Counter0Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.RW0PRADCPower Reduction ADCWriting a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.RW0RSTFLRReset Flag Register$3B$3Bio_cpu.bmpYWDRFWatchdog Reset FlagThis bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.RW0EXTRFExternal Reset FlagThis bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.RW0PORFPower-on Reset FlagThis bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.RW0NVMCSRNon-Volatile Memory Control and Status Register$32$32io_cpu.bmpYNVMBSYNon-Volatile Memory BusyThis bit indicates the NVM Memory (Flash memory and Lock Bits) is busy, being programmed. This bit is set when a program operation is started, and it remains set until the operation has been completed.RW0NVMCMDNon-Volatile Memory Command$33$33io_cpu.bmpNNVMCMD5RW0NVMCMD4RW0NVMCMD3RW0NVMCMD2RW0NVMCMD1RW0NVMCMD0RW0MCUCRMCU Control Register$3A$3Aio_cpu.bmpNISC01RW0ISC00RW0BODSRW0SM2RW0SM1RW0SM0RW0SERW0GIMSKGeneral Interrupt Mask Register$0C$0Cio_cpu.bmpNPCIE2RW0PCIE1RW0PCIE0RW0INT0RW0GIFRGeneral Interrupt Flag Register$0B$0Bio_cpu.bmpNPCIF2RW0PCIF1RW0PCIF0RW0INTF0RW0RAMARRAM Address Register$20$20io_cpu.bmpNRAMAR7RAMAR70RAMAR6RW0RAMAR5RW0RAMAR4RW0RAMAR3RW0RAMAR2RW0RAMAR1RW0RAMAR0RW0RAMDRRAM Data Register$1F$1Fio_cpu.bmpNRAMDR7RAMDR70RAMDR6RW0RAMDR5RW0RAMDR4RW0RAMDR3RW0RAMDR2RW0RAMDR1RW0RAMDR0RW0[PCMSK2:PCMSK1:PCMSK0]io_ext.bmpPCMSK2Pin Change Mask Register 2$1A$1Aio_flag.bmpYPCINT17Pin Change Enable Mask 3Each PCINT17..12 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is set and the PCIE2 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT16Pin Change Enable Mask 3Each PCINT17..12 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is set and the PCIE2 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT15Pin Change Enable Mask 3Each PCINT17..12 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is set and the PCIE2 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT14Pin Change Enable Mask 2Each PCINT17..12 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is set and the PCIE2 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT13Pin Change Enable Mask 1Each PCINT17..12 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is set and the PCIE2 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT12Pin Change Enable Mask 0Each PCINT17..12 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is set and the PCIE2 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..12 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCMSK1Pin Change Mask Register 1$0A$0Aio_flag.bmpYPCINT11Pin Change Enable Mask 3Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT10Pin Change Enable Mask 2Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT9Pin Change Enable Mask 1Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT8Pin Change Enable Mask 0Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCMSK0Pin Change Mask Register 0$09$09io_flag.bmpYPCINT7Pin Change Enable Mask 3Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT6Pin Change Enable Mask 3Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT5Pin Change Enable Mask 3Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT4Pin Change Enable Mask 3Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT3Pin Change Enable Mask 3Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT2Pin Change Enable Mask 2Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT1Pin Change Enable Mask 1Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0PCINT0Pin Change Enable Mask 0Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.RW0[PORTCR:PUEB:PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTCRPort Control Register$08$08io_flag.bmpYADC11DRW0ADC10DRW0ADC9DRW0ADC8DRW0BBMCBreak-Before-Make Mode EnableRW0BBMBBreak-Before-Make Mode EnableRW0BBMABreak-Before-Make Mode EnableRW0PUEBPull-up Enable Control Register$07$07io_flag.bmpNPUEB3RW0PUEB2RW0PUEB1RW0PUEB0RW0DDRBData Direction Register, Port B$05$05io_flag.bmpNDDB3RW0DDB2RW0DDB1RW0DDB0RW0PINBPort B Data register$04$04io_port.bmpNPINB3RW0PINB2RW0PINB1RW0PINB0RW0PORTBInput Pins, Port B$06$06io_port.bmpNPORTB3RW0PORTB2RW0PORTB1RW0PORTB0RW0[PORTCR:PUEC:PORTC:DDRC:PINC]io_port.bmpAVRSimIOPort.SimIOPortPORTCRPort Control Register$08$08io_flag.bmpYADC11DRW0ADC10DRW0ADC9DRW0ADC8DRW0BBMCBreak-Before-Make Mode EnableRW0PUECPull-up Enable Control Register$1E$1Eio_flag.bmpNPUEC5RW0PUEC4RW0PUEC3RW0PUEC2RW0PUEC1RW0PUEC0RW0PORTCPort C Data Register$1D$1Dio_port.bmpNPORTC5RW0PORTC4RW0PORTC3RW0PORTC2RW0PORTC1RW0PORTC0RW0DDRCData Direction Register, Port C$1C$1Cio_flag.bmpNDDC5RW0DDC4RW0DDC3RW0DDC2RW0DDC1RW0DDC0RW0PINCPort C Input Pins$1B$1Bio_port.bmpNPINC5RW0PINC4RW0PINC3RW0PINC2RW0PINC1RW0PINC0RW0[TCCR0A:TCCR0B:TCCR1A:TCNT1H:TCNT1L:OCR1A:OCR1B:TIMSK:TIFR:TCNT0:OCR0A:OCR0B]
[TCNT0H:TCNT0L]
io_timer.bmpTCCR0ATimer/Counter 0 Control Register A$19$19io_flag.bmpYCOM0A1Compare Output Mode for Channel A bit 1The COM0A1:0 and COM0B1:0 control the behaviour of Output Compare pins OC0A and OC0B, respectively. If one or both COM0A1:0 bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. Similarly, if one or both COM0B1:0 bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver.RW0COM0A0Compare Output Mode for Channel A bit 0The COM0A1:0 and COM0B1:0 control the behaviour of Output Compare pins OC0A and OC0B, respectively. If one or both COM0A1:0 bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. Similarly, if one or both COM0B1:0 bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver.RW0COM0B1Compare Output Mode for Channel B bit 1The COM0A1:0 and COM0B1:0 control the behaviour of Output Compare pins OC0A and OC0B, respectively. If one or both COM0A1:0 bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. Similarly, if one or both COM0B1:0 bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver.W0COM0B0Compare Output Mode for Channel B bit 0The COM0A1:0 and COM0B1:0 control the behaviour of Output Compare pins OC0A and OC0B, respectively. If one or both COM0A1:0 bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. Similarly, if one or both COM0B1:0 bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driveRW0WGM01Waveform Generation ModeCombined with WGM03:2 bits of TCCR0B, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform to generate. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation(PWM) modes.RW0WGM00Waveform Generation ModeCombined with WGM03:2 bits of TCCR0B, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform to generate. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation(PWM) modes.RW0TCCR0BTimer/Counter 0 Control Register B$18$18io_flag.bmpYFOC0AForce Output Compare AThe FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare.A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.The FOC0A bit always reads as zero.RW0FOC0BForce Output Compare BThe FOC0B bit is only active when the WGM bits specify a non-PWM mode.However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare.A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.RW0TSMTimer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting.RW0PSRPrescaler Reset Timer/CounterWhen this bit is one, the Timer/Counter prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.RW0WGM02Waveform Generation ModeSee the description in the “TCCR0A – Timer/Counter Control Register A” on page 72.RW0CS02Clock SelectThe three Clock Select bits set the clock source to be used by the Timer/Counter.RW0CS01Clock SelectThe three Clock Select bits set the clock source to be used by the Timer/CounterRW0CS00Clock SelectThe three Clock Select bits set the clock source to be used by the Timer/CounterRWCLK_SEL_3BIT_EXT0TCCR1ATimer/Counter1 Control Register A$24$24io_flag.bmpYTCW1Timer/Counter1 WidthRW0ICEN1Input Capture Mode EnableRW0ICNC1: Input Capture Noise CancelerRW0ICES1Input Capture Edge SelectRW0CTC1Waveform Generation ModeRW0CS12The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer1.RW0CS11PWM11The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer1.RW0CS10PWM10The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer1.RW0TCNT1HTimer/Counter1 HighThe two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare.$27$27io_timer.bmpNTCNT1_15RW0TCNT1_14RW0TCNT1_13RW0TCNT1_12RW0TCNT1_11RW0TCNT1_10RW0TCNT1_9RW0TCNT1_8RW0TCNT1LTimer/Counter1 LowThe two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare.$23$23io_timer.bmpNTCNT1_7RW0TCNT1_6RW0TCNT1_5RW0TCNT1_4RW0TCNT1_3RW0TCNT1_2RW0TCNT1_1RW0TCNT1_0RW0OCR1ATimer/Counter 1 Output Compare Register AThe Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers.$22$22io_timer.bmpNOCR1A7RW0OCR1A6RW0OCR1A5RW0OCR1A4RW0OCR1A3RW0OCR1A2RW0OCR1A1RW0OCR1A0RW0OCR1BTimer/Counter 1 Output Compare Register BThe Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers.$21$21io_timer.bmpNOCR1B7RW0OCR1B6RW0OCR1B5RW0OCR1B4RW0OCR1B3RW0OCR1B2RW0OCR1B1RW0OCR1B0RW0TIMSKTimer Interrupt Mask Register$26$26io_flag.bmpYICIE1Input Capture Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 66.) is executed when the ICF1 Flag, located in TIFR, is set.RW0OCIE1BOutput Compare B Match Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF1B flag, located in TIFR, is set.RW0OCIE1AOutput Compare A Match Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF0A flag, located in TIFR0, is set.RW0TOIE1Overflow Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV1 flag, located in TIFR1, is set.RW0OCIE0BTimer/Counter Output Compare Match B Interrupt EnableWhen the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR.RW0OCIE0ATimer/Counter0 Output Compare Match A Interrupt EnableWhen the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter Interrupt Flag Register – TIFR.RW0TOIE0Timer/Counter0 Overflow Interrupt EnableWhen the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.RW0TIFROverflow Interrupt Enable$25$25io_flag.bmpYICF1Input Capture FlagThis flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value.ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location.RW0OCF1BTimer Output Compare Flag 1BThis flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed.Alternatively, OCF1B can be cleared by writing a logic one to its bit location.RW0OCF1ATimer Output Compare Flag 1AThis flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A).Note that a Forced Output Compare (1A) strobe will not set the OCF1A flag.OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.RW0TOV1Timer Overflow FlagThe setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,the TOV1 flag is set when the timer overflows. See Table 12-5 on page 102 for the TOV1 flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.RW0OCF0BOutput Compare Flag 0 BThe OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.RW0OCF0AOutput Compare Flag 0 AThe OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.RW0TOV0Timer/Counter0 Overflow FlagThe bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. See Table 11-8 on page 75 and “Waveform Generation Mode Bit Description” on page 75.RW0TCNT0Timer/Counter0The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.$17$17io_timer.bmpNTCNT0_7RW0TCNT0_6RW0TCNT0_5RW0TCNT0_4RW0TCNT0_3RW0TCNT0_2RW0TCNT0_1RW0TCNT0_0RW0OCR0ATimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$16$16io_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0OCR0BTimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$15$15io_timer.bmpNOCR0B_7RW0OCR0B_6RW0OCR0B_5RW0OCR0B_4RW0OCR0B_3RW0OCR0B_2RW0OCR0B_1RW0OCR0B_0RW0[PORTCR:PUEA:PORTA:DDRA:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTCRPort Control Register$08$08io_flag.bmpYBBMABreak-Before-Make Mode EnableRW0PUEAPull-up Enable Control Register$03$03io_flag.bmpNPUEA7RW0PUEA6RW0PUEA5RW0PUEA4RW0PUEA3RW0PUEA2RW0PUEA1RW0PUEA0RW0PORTAPort C Data Register$02$02io_port.bmpNPORTA7RW0PORTA6RW0PORTA5RW0PORTA4RW0PORTA3RW0PORTA2RW0PORTA1RW0PORTA0RW0DDRAData Direction Register, Port C$01$01io_flag.bmpNDDC7RW0DDC6RW0DDC5RW0DDC4RW0DDC3RW0DDC2RW0DDC1RW0DDC0RW0PINAPort C Input Pins$00$00io_port.bmpNPINA7RW0PINA6RW0PINA5RW0PINA4RW0PINA3RW0PINA2RW0PINA1RW0PINA0RW0[STK600:SIMULATOR2]libATtiny40.dll