[ADMIN:FUSE:LOCKBIT:MEMORY:PROGRAMMING:CORE:INTERRUPT_VECTOR:PACKAGE:IO_MODULE:ICE_SETTINGS] ATtiny28 4MHZ 1 RELEASED $1E $91 $07 [LOW] 17 5 0x10 0x00 Internal load capacitors between XTAL1/XTAL2 and GND 0x0F 0x0F CKSEL=1111 External Crystal / Ceramic Resonator 0x0F 0x0E CKSEL=1110 External Crystal / Ceramic Resonator 0x0F 0x0D CKSEL=1101 External Crystal / Ceramic Resonator 0x0F 0x0C CKSEL=1100 External Crystal / Ceramic Resonator 0x0F 0x0B CKSEL=1011 External Crystal / Ceramic Resonator 0x0F 0x0A CKSEL=1010 External Crystal / Ceramic Resonator 0x0F 0x09 CKSEL=1001 External Low-Frequency Crystal 0x0F 0x08 CKSEL=1000 External Low-Frequency Crystal 0x0F 0x07 CKSEL=0111 External RC Ocsillator 0x0F 0x06 CKSEL=0110 External RC Ocsillator 0x0F 0x05 CKSEL=0101 External RC Ocsillator 0x0F 0x04 CKSEL=0100 Internal RC Ocsillator 0x0F 0x03 CKSEL=0011 Internal RC Ocsillator 0x0F 0x02 CKSEL=0010 Internal RC Ocsillator ; default value 0x0F 0x01 CKSEL=0001 External Clock 0x0F 0x00 CKSEL=0000 External Clock [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x06 0x06 Mode 1: No memory lock features enabled 0x06 0x04 Mode 2: Further programming disabled 0x06 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit AVRSimMemory8bit.SimMemory8bit 2048 0 0 NA 0 NA $00 $3F NA NA $20 $5F $3F NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1B NA $0f 0x01 0x02 0x04 0x08 $1A NA 0x01 0x02 0x04 0x08 $19 NA $b 0x01 0x02 0x08 $16 NA $ff 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $12 NA $ff 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $11 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $10 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $08 NA 0x01 0x02 0x08 0x10 0x20 0x80 $07 NA 0x01 0x02 0x08 0x10 0x20 0x80 $06 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $05 NA 0x10 0x40 0x80 $04 NA 0x01 0x02 0x04 0x08 0x10 0x80 $03 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $02 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $01 NA 0x01 0x02 0x04 0x08 0x10 $00 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x00,1.2 MHz 0 0 V0E AVRSimCoreV0.SimCoreV0 [] [] [] 32 $00 $1B $1A $1D $1C $1F $1E 6 $000 RESET External Reset, Power-on Reset and Watchdog Reset $001 INT0 External Interrupt 0 $002 INT1 External Interrupt 1 $003 LOW-LEVEL I/O PINS Low-level Input on Port B $004 TIMER0_OVF Timer/Counter0 Overflow $005 ANA_COMP Analog Comparator [TQFP] 32 [PD3] [PD4] [NC] [VCC] [GND] [NC] [XTAL1] [XTAL2] [PD5] [PD6] [PD7] [AIN0:PB0] [AIN1:PB1] [T0:PB2] [INT0:PB3] [INT1:PB4] [PB5] [VCC] [NC] [NC] [GND] [NC] [PB6] [PB7] [PA2:IR] [PA3] [PA1] [PA0] [RESET] [PD0] [PD1] [PD2] [PORTD:CPU:ANALOG_COMPARATOR:TIMER_COUNTER_0:WATCHDOG:EXTERNAL_INTERRUPT:PORTA:PORTB:MODULATOR] [PORTD:DDRD:PIND] io_port.bmp AVRSimIOPort.SimIOPort PORTD Port D Data Register $12 NA io_port.bmp N PORTD7 Port D Data Register bit 7 RW 0 PORTD6 Port D Data Register bit 6 RW 0 PORTD5 Port D Data Register bit 5 RW 0 PORTD4 Port D Data Register bit 4 RW 0 PORTD3 Port D Data Register bit 3 RW 0 PORTD2 Port D Data Register bit 2 RW 0 PORTD1 Port D Data Register bit 1 RW 0 PORTD0 Port D Data Register bit 0 RW 0 DDRD Port D Data Direction Register $11 NA io_flag.bmp N DDD7 Port D Data Direction Register bit 7 RW 0 DDD6 Port D Data Direction Register bit 6 RW 0 DDD5 Port D Data Direction Register bit 5 RW 0 DDD4 Port D Data Direction Register bit 4 RW 0 DDD3 Port D Data Direction Register bit 3 RW 0 DDD2 Port D Data Direction Register bit 2 RW 0 DDD1 Port D Data Direction Register bit 1 RW 0 DDD0 Port D Data Direction Register bit 0 RW 0 PIND Port D Input Pins The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. $10 NA io_port.bmp N PIND7 Port D Input Pins bit 7 R 0 PIND6 Port D Input Pins bit 6 R 0 PIND5 Port D Input Pins bit 5 R 0 PIND4 Port D Input Pins bit 4 R 0 PIND3 Port D Input Pins bit 3 R 0 PIND2 Port D Input Pins bit 2 R 0 PIND1 Port D Input Pins bit 1 R 0 PIND0 Port D Input Pins bit 0 R 0 [SREG:ICR:MCUCS:OSCCAL] io_cpu.com SREG Status Register $3F NA io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 ICR Interrupt Control Register $06 NA io_cpu.bmp Y ICS11 Interrupt Sense Control 1 bit 1 RW 0 ICS10 Interrupt Sense Control 1 bit 0 RW INTERRUPT_SENSE_CONTROL2 0 ISC01 Interrupt Sense Control 0 bit 1 RW 0 ISC00 Interrupt Sense Control 0 bit 0 RW INTERRUPT_SENSE_CONTROL2 0 MCUCS MCU Control and Status Register The MCU Control and Status Register contains control and status bits for general MCU functions. $07 NA io_cpu.bmp Y PLUPB Pull-up Enable Port B When the PLUPB bit is set (one), pull-up resistors are enabled on all Port B input pins. RW 0 SE Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction. RW 0 SM Sleep Mode This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the section “Sleep Modes” on page 25. RW 0 WDRF Watchdog Reset Flag RW 0 EXTRF External Reset Flag After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged. RW 0 PORF Power-On Reset Flag This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged RW 0 OSCCAL Status Register $00 NA io_sreg.bmp N CAL7 Oscillator Calibration Value Bit 7 RW 0 CAL6 Oscillator Calibration Value Bit 6 RW 0 CAL5 Oscillator Calibration Value Bit 5 RW 0 CAL4 Oscillator Calibration Value Bit 4 RW 0 CAL3 Oscillator Calibration Value Bit 3 RW 0 CAL2 Oscillator Calibration Value Bit 2 RW 0 CAL1 Oscillator Calibration Value Bit 1 RW 0 CAL0 Oscillator Calibration Value Bit 0 RW 0 [ACSR] io_analo.bmp The analog comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Com-parator Output, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Inter-rupt triggering on comparator output rise, fall or toggle ACSR Analog Comparator Control And Status Register $08 NA io_analo.bmp Y ACD Analog Comparator Disable When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACO Analog Comparator Output When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. R 0 ACI Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When Cleared (Zero), the interrupt is disabled. RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW ANALOG_COMP_INTERRUPT 0 [ICR:IFR:TCCR0:TCNT0] io_timer.bmp t81 The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions ICR Interrupt Control Register $06 NA io_flag.bmp Y TOIE0 Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 IFR Interrupt Flag register $05 NA io_flag.bmp Y TOV0 Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. RW 0 TCCR0 Timer/Counter0 Control Register $04 NA io_flag.bmp Y FOV0 Force Overflow Writing a logical "1" to this bit forces a change on the overflow output pin PA2 according to the values already set in OOM01 and OOM00. RW 0 OOM01 Overflow Output Mode, Bit 1 The OOM01 and OOM00 control bits determine any output pin action following an overflow or a forced overflow in Timer/Counter0. RW 0 OOM00 Overflow Output Mode, Bit 0 The OOM01 and OOM00 control bits determine any output pin action following an overflow or a forced overflow in Timer/Counter0. RW CLK_COMP_MATCH_OUT_MODE 0 CS02 Clock Select0 bit 2 RW 0 CS01 Clock Select0 bit 1 RW 0 CS00 Clock Select0 bit 0 RW CLK_SEL_3BIT_EXT_MOD 0 TCNT0 Timer Counter 0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. $03 NA io_timer.bmp N TCNT07 Timer Counter 0 bit 7 RW 0 TCNT06 Timer Counter 0 bit 6 RW 0 TCNT05 Timer Counter 0 bit 5 RW 0 TCNT04 Timer Counter 0 bit 4 RW 0 TCNT03 Timer Counter 0 bit 3 RW 0 TCNT02 Timer Counter 0 bit 2 RW 0 TCNT01 Timer Counter 0 bit 1 RW 0 TCNT00 Timer Counter 0 bit 0 RW 0 [WDTCR] io_watch.bmp WDTCR Watchdog Timer Control Register $01 NA io_flag.bmp Y WDTOE WDDE RW This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure. RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW WDOG_TIMER_PRESCALE_3BITS 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [ICR:IFR] io_ext.bmp ICR Interrupt Control Register $06 NA io_flag.bmp Y INT1 External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.The interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) define whether the external interrupt is activated on rising or falling edge, on pin change or low level of the INT0 pin. RW 0 INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.The interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) define whether the external interrupt is activated on rising or falling edge, on pin change or low level of the INT0 pin. RW 0 LLIE Low-level Input Interrupt Enable When the LLIE is set (one) and the I-bit in the status register (SREG) is set (one), the interrupt on low-level input is activated. Any of the Port B pins pulled low will then cause an interrupt. RW 0 IFR Interrupt Flag register $05 NA io_flag.bmp Y INTF1 External Interrupt Flag 1 When the INT1 bit is set (one) and I-bit in the Status Register (SREG) is set (one), the external pin interrupt 1 is enabled. RW 0 INTF0 External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in ICR are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 [PORTA:PACR:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register $1B NA io_port.bmp N PORTA3 Port A Data Register bit 3 RW 0 PORTA2 Port A Data Register bit 2 RW 0 PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 PACR Port A Control Register $1A NA io_flag.bmp N DDA3 Data Direction Port A, bit 3 RW 0 PA2HC PORTA2 High Current Enable RW 0 DDA1 Data Direction Port A, bit 1 RW 0 DDA0 Data Direction Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. $19 NA io_port.bmp N PINA3 Input Pins, Port A bit 3 R Hi-Z PINA1 Input Pins, Port A bit 1 R Hi-Z PINA0 Input Pins, Port A bit 0 R Hi-Z [PINB] io_port.bmp AVRSimIOPort.SimIOPort PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. $16 NA io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [MODCR] io_poer.bmp MODCR Modulation Control Register $02 NA io_flag.bmp Y ONTIM4 Modulation On-time Bit 4 ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low) RW 0 OTIM3 Modulation On-time Bit 3 ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low) RW 0 ONTIM2 Modulation On-time Bit 2 ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low) RW 0 ONTIM1 Modulation On-time Bit 1 ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low) RW 0 ONTIM0 Modulation On-time Bit 0 ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low) RW 0 MCONF2 Modulation Configuration Bit 2 MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle. RW 0 MCONF1 Modulation Configuration Bit 1 MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle. RW 0 MCONF0 Modulation Configuration Bit 0 MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle. RW 0 [STK500:STK500_2:SIMULATOR:AVRDragon:STK600] 0x22 1 1 0 0x00 0x00 0x00 0 0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00 100 0 0 0 0 0 0 15 15 0 10 5 0x00 256 256 5 0x00 256 256 0 5 0 5 AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 8 AVRSimIOPort.SimIOPort 0x0f N AVRSimIOPort.SimIOPort 0xff N AVRSimIOPort.SimIOPort 0xff N AVRSimIOExtInterrupt.SimIOExtInterrupt 0x01 0x06 0x40 0x05 0x40 0x16 0x08 0x06 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x02 0x06 0x80 0x05 0x80 0x16 0x10 0x06 0x0c AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x03 0x06 0x20 0x05 0x00 0x00 0x16 0xFF AVRSimIOTimert81.SimIOTimert81 0x04 0x16 0x04 AVRSimAC.SimIOAC 0x05 0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00 100 0 0 0 0 0 0 15 15 0 2 5 0x00 256 256 5 0x00 256 256 0 1 0 1