[ADMIN:CORE:FUSE:INTERRUPT_VECTOR:LOCKBIT:PACKAGE:MEMORY:PROGRAMMING:IO_MODULE:ICE_SETTINGS] ATtiny167 16MHZ 1 RELEASED $1E $94 $87 1 0x31 0 0 0x00 V2 AVRSimCoreV2.SimCoreV2 [lpm rd,z+] [] [] 32 $00 $1B $1A $1D $1C $1F $1E [LOW:HIGH:EXTENDED] 46 8 0x80 0x00 Divide clock by 8 internally; [CKDIV8=0] 0x40 0x00 Clock output on PORTB5; [CKOUT=0] 0x3F 0x00 Ext. Clock - XTAL1; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00] 0x3F 0x10 Ext. Clock - XTAL1; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0000 SUT=01] 0x3F 0x20 Ext. Clock - XTAL1; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0000 SUT=10] 0x3F 0x02 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00] 0x3F 0x12 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0010 SUT=01] 0x3F 0x22 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0010 SUT=10]; default value 0x3F 0x03 WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0011 SUT=00] 0x3F 0x13 WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0011 SUT=01] 0x3F 0x23 WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0011 SUT=10] 0x3F 0x04 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1024 CK 4 ms; [CKSEL=0100 SUT=00] 0x3F 0x14 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1024 CK + 64 ms; [CKSEL=0100 SUT=01] 0x3F 0x24 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32768 CK + 64 ms; [CKSEL=0100 SUT=10] 0x3F 0x08 Ext. Ceramic Res.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F 0x18 Ext. Ceramic Res.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F 0x28 Ext. Ceramic Res.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F 0x38 Ext. Ceramic Res.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F 0x09 Ext. Ceramic Res.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F 0x19 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F 0x29 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F 0x39 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F 0x0A Ext. Ceramic Res.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F 0x1A Ext. Ceramic Res.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F 0x2A Ext. Ceramic Res.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F 0x3A Ext. Ceramic Res.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F 0x0B Ext. Ceramic Res.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F 0x1B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F 0x2B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F 0x3B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F 0x0C Ext. Ceramic Res.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F 0x1C Ext. Ceramic Res.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F 0x2C Ext. Ceramic Res.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F 0x3C Ext. Ceramic Res.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F 0x0D Ext. Ceramic Res.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F 0x1D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F 0x2D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F 0x3D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F 0x0E Ext. Ceramic Res.; Frequency 8.0-16.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F 0x1E Ext. Ceramic Res.; Frequency 8.0-16.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F 0x2E Ext. Ceramic Res.; Frequency 8.0-16.0 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F 0x3E Ext. Ceramic Res.; Frequency 8.0-16.0 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F 0x0F Ext. Ceramic Res.; Frequency 8.0-16.0 MHz; Start-up time PWRDWN/RESET: 1024 CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F 0x1F Ext. Crystal Osc.; Frequency 8.0-16.0 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F 0x2F Ext. Crystal Osc.; Frequency 8.0-16.0 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F 0x3F Ext. Crystal Osc.; Frequency 8.0-16.0 MHz; Start-up time PWRDWN/RESET: 16384 CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] CKSEL0 Select Clock source 0 CKSEL1 Select Clock source 1 CKSEL2 Select Clock source 0 CKSEL3 Select Clock source 0 SUT0 Select start-up time 0 SUT1 Select start-up time 1 CKOUT Clock Output Enable 1 CKDIV8 Divide clock by 8 0 13 8 0x80 0x00 Reset Disabled (Enable PB7 as i/o pin); [RSTDISBL=0] 0x40 0x00 Debug Wire enable; [DWEN=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x10 0x00 Watch-dog Timer always ON; [WDTON=0] 0x08 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x07 0x04 Brown-out detection level at VCC=4.3 V; [BODLEVEL=100] 0x07 0x05 Brown-out detection level at VCC=2.7 V; [BODLEVEL=101] 0x07 0x06 Brown-out detection level at VCC=1.8 V; [BODLEVEL=110] 0x07 0x03 Brown-out detection level at VCC=2.3 V; [BODLEVEL=011] 0x07 0x02 Brown-out detection level at VCC=2.2 V; [BODLEVEL=010] 0x07 0x01 Brown-out detection level at VCC=1.9 V; [BODLEVEL=001] 0x07 0x00 Brown-out detection level at VCC=2.0 V; [BODLEVEL=000] 0x07 0x07 Brown-out detection disabled; [BODLEVEL=111] BODLEVEL0 Brown-out Detector trigger level 1 BODLEVEL1 Brown-out Detector trigger level 1 BODLEVEL2 Brown-out Detector trigger level 1 EESAVE EEPROM memory is preserved through the Chip Erase 1 WDTON Watchdog Timer always ON 1 SPIEN Enable Serial Program and Data Downloading 0 DWEN DebugWIRE Enable 1 RSTDISBL External Reset disable 1 SELFPRGEN Self-Programming Enable 1 1 1 0x01 0x00 Self Programming enable; [SELFPRGEN=0] 20 AVRSimInterrupt.SimInterrupt $000 RESET External Reset, Power-on Reset and Watchdog Reset $002 INT0 External Interrupt Request 0 $004 INT1 External Interrupt Request 1 $006 PCINT0 Pin Change Interrupt Request 0 $008 PCINT1 Pin Change Interrupt Request 1 $00A WDT Watchdog Time-Out Interrupt $00C TIMER1_CAPT Timer/Counter1 Capture Event $00E TIMER1_COMPA Timer/Counter1 Compare Match 1A $010 TIMER1_COMPB Timer/Counter1 Compare Match 1B $012 TIMER1_OVF Timer/Counter1 Overflow $014 TIMER0_COMPA Timer/Counter0 Compare Match 0A $016 TIMER0_OVF Timer/Counter0 Overflow $018 LIN_TC LIN Transfer Complete $01A LIN_ERR LIN Error $01C SPI_STC SPI Serial Transfer Complete $01E ADC ADC Conversion Complete $020 EE_RDY EEPROM Ready $022 ANA_COMP Analog Comparator $024 USI_START USI Start $0026 USI_OVF USI Overflow [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit [SOIC] 20 [RXLIN:RXD:ADC0:PCINT0:PA0] RXLIN (LIN Receive Pin). RXD (UART Receive Pin). ADC0 (ADC Input Channel 0). PCINT0 (Pin Change Interrupt 0). PORTA0. [TXLIN:TXD:ADC1:PCINT1:PA1] TXLIN (LIN Transmit Pin). RXD (UART Receive Pin). ADC0 (ADC Input Channel 0). PCINT0 (Pin Change Interrupt 0). PORTA1. [MISO:DO:OC0A:ADC2:PCINT2:PA2] MISO (SPI Master Input / Slave Output). DO (Three-wire Mode USI Alternate Data Output). OC0A (Output Compare and PWM Output A for Timer/Counter0). ADC2 (ADC Input Channel 2). PCINT2 (Pin Change Interrupt 2). PORTA2. [INT1:ISRC:ADC3:PCINT3:PA3] INT1 (External Interrupt1 Input). ISRC (Current Source Pin). ADC3 (ADC Input Channel 3). PCINT3 (Pin Change Interrupt 3). PORTA3. [AVCC] Analog Supply Voltage. [AGND] Analog Ground. [MOSI:SDA:DI:ICP1:ADC4:PCINT4:PA4] MOSI (SPI Master Output / Slave Input). SDA (Two-wire Mode USI Alternate Data Input / Output). DI (Three-wire Mode USI Alternate Data Input).ICP1 (Timer/Counter1 Input Capture Trigger). ADC4 (ADC Input Channel 4). PCINT4 (Pin Change Interrupt 4). PORTA4. [SCK:SCL:USCK:T1:ADC5:PCINT5:PA5] SCK (SPI Master Clock). SCL (Two-wire Mode USI Alternate Clock Input). USCK (Three-wire Mode USI Alternate Clock Input). T1 (Timer/Counter1 Clock Input). ADC5 (ADC Input Channel 5). PCINT5 (Pin Change Interrupt 5). PORTA5. [SS:AIN0:ADC6:PCINT6:PA6] SS (Active Low SPI Slave Select Input). AIN0 (Analog Comparator Negative Input). ADC6 (ADC Input Channel 6). PCINT6 (Pin Change Interrupt 6). PORTA6. [AREF:XREF:AIN1:ADC7:PCINT7:PA7] AREF (External Voltage Reference Input). XREF (Internal Voltage Reference Output). AIN1 (Analog Comparator Positive Input). ADC7 (ADC Input Channel 7). PCINT7 (Pin Change Interrupt 7). PORTA7. [dW:RESET:OC1BX:ADC10:PCINT15:PB7] dW (debugWIRE I/O). RESET (Active Low Reset pin). OC1BX (Output Compare and PWM Output B-X for Timer/Counter1). ADC10 (ADC Input Channel 10). PCINT15 (Pin Change Interrupt 15). PORTB7. [INT0:OC1AX:ADC9:PCINT14:PB6] INT0 (External Interrupt0 Input). OC1AX (Output Compare and PWM Output A-X for Timer/Counter1). ADC9 (ADC Input Channel 9). PCINT14 (Pin Change Interrupt 14). PORTB6. [CLKO:XTAL2:OC1BW:ADC8:PCINT13:PB5] CLKO (System clock output). XTAL2 (Chip clock Oscillator pin 2). OC1BW (Output Compare and PWM Output B-W for Timer/Counter1). ADC8 (ADC Input Channel 8). PCINT13 (Pin Change Interrupt 13). PORTB5. [CLKI:XTAL1:OC1AW:PCINT12:PB4] CLKI (External clock input). XTAL1 (Chip clock Oscillator pin 1). OC1AW (Output Compare and PWM Output A-W for Timer/Counter1). PCINT12 (Pin Change Interrupt 12). PORTB4. [VCC] Supply Voltage. [GND] Ground. [OC1BV:PCINT11:PB3] OC1BV (Output Compare and PWM Output B-V for Timer/Counter1). PCINT11 (Pin Change Interrupt 11). PORTB3. [SCL:USCK:OC1AV:PCINT10:PB2] SCL (Two-wire Mode USI Default Clock Input). USCK (Three-wire Mode USI Default Clock Input). OC1AV (Output Compare and PWM Output A-V for Timer/Counter1). PCINT10 (Pin Change Interrupt 10). PORTB2. [DO:OC1BU:PCINT9:PB1] DO (Three-wire Mode USI Default Data Output). OC1BU (Output Compare and PWM Output B-U for Timer/Counter1). PCINT9 (Pin Change Interrupt 9). PORTB1. [SDA:DI:OC1AU:PCINT8:PB0] SDA (Two-wire Mode USI Default Data Input / Output). DI (Three-wire Mode USI Default Data Input). OC1AU (Output Compare and PWM Output A-U for Timer/Counter1). PCINT8 (Pin Change Interrupt 8). PORTB0. AVRSimMemory8bit.SimMemory8bit 16384 512 512 $0100 0 NA $0000 $003F $0060 $00FF $0020 $00FF NA $D2 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $D1 0x01 0x02 0x04 0x08 NA $D0 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $CF 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $CE 0x01 0x02 0x04 0x08 NA $CD 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $CC 0x01 0x02 0x04 0x08 0x10 0x20 0x80 NA $CB 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $CA 0x01 0x02 0x04 0x08 NA $C9 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $C8 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $BC 0x01 NA $BB 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $BA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $B9 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $B8 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $B6 0x01 0x02 0x08 0x10 0x20 0x40 NA $8B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $8A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $89 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $88 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $87 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $86 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $85 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $84 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $83 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $82 0x40 0x80 NA $81 0x01 0x02 0x04 0x08 0x10 0x40 0x80 NA $80 0x01 0x02 0x10 0x20 0x40 0x80 NA $7F 0x01 0x02 0x04 NA $7E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $7C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $7B 0x01 0x02 0x04 0x80 0x10 0x20 0x40 NA $7A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $79 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $78 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $77 0x02 0x04 0x01 NA $6F 0x01 0x02 0x04 0x20 NA $6E 0x01 0x02 NA $6C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $6B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $69 0x01 0x02 0x04 0x08 NA $68 0x01 0x02 NA $66 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $64 0x01 0x02 0x04 0x08 0x10 0x20 NA $63 0x01 0x02 0x04 0x08 0x10 0x20 0x40 NA $62 0x01 0x02 0x04 0x08 0x10 0x80 NA $61 0x01 0x02 0x04 0x08 0x80 NA $60 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3F $5F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3E $5E 0x01 0x02 0x04 $3D $5D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $37 $57 0x01 0x02 0x04 0x08 0x10 0x20 0x40 $35 $55 0x10 0x20 0x40 $34 $54 0x01 0x02 0x04 0x08 $33 $53 0x01 0x02 0x04 $31 $51 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $30 $50 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2E $4E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2D $4D 0x01 0x40 0x80 $2C $4C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2B $4B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2A $4A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $28 $48 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $27 $47 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $26 $46 0x01 0x02 0x04 0x80 $25 $45 0x01 0x02 0x40 0x80 $23 $43 0x01 0x02 0x80 $22 $42 0x01 $21 $41 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $20 $40 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1F $3F 0x01 0x02 0x04 0x08 0x10 0x20 $1E $3E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1D $3D 0x01 0x02 $1C $3C 0x01 0x02 $1B $3B 0x01 0x02 $16 $36 0x01 0x02 0x04 0x20 $15 $35 0x01 0x02 $12 $32 0x01 0x04 0x10 0x20 $05 $25 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $04 $24 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $03 $23 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $02 $22 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $01 $21 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $00 $20 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $0 $1FFF $0 $0 64 0xff,0xdf 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x00,WARNING! Enabling the debugWIRE interface will disable the ISP interface! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x00,WARNING! Enabling the debugWIRE interface will disable the ISP interface! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 0x00,8.0 MHz 128 4 [PORTA:PORTB:LINUART:USI:TIMER_COUNTER_0:TIMER_COUNTER_1:WATCHDOG:EEPROM:SPI:AD_CONVERTER:CURRENT_SOURCE:ANALOG_COMPARATOR:EXTERNAL_INTERRUPT:BOOT_LOAD:CPU] [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register $02 $22 io_port.bmp N PORTA7 Port A Data Register bit 7 RW 0 PORTA6 Port A Data Register bit 6 RW 0 PORTA5 Port A Data Register bit 5 RW 0 PORTA4 Port A Data Register bit 4 RW 0 PORTA3 Port A Data Register bit 3 RW 0 PORTA2 Port A Data Register bit 2 RW 0 PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 DDRA Port A Data Direction Register $01 $21 io_flag.bmp N DDA7 Data Direction Register, Port A, bit 7 RW 0 DDA6 Data Direction Register, Port A, bit 6 RW 0 DDA5 Data Direction Register, Port A, bit 5 RW 0 DDA4 Data Direction Register, Port A, bit 4 RW 0 DDA3 Data Direction Register, Port A, bit 3 RW 0 DDA2 Data Direction Register, Port A, bit 2 RW 0 DDA1 Data Direction Register, Port A, bit 1 RW 0 DDA0 Data Direction Register, Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. $00 $20 io_port.bmp N PINA7 Input Pins, Port A bit 7 RW Hi-Z PINA6 Input Pins, Port A bit 6 RW Hi-Z PINA5 Input Pins, Port A bit 5 RW Hi-Z PINA4 Input Pins, Port A bit 4 RW Hi-Z PINA3 Input Pins, Port A bit 3 RW Hi-Z PINA2 Input Pins, Port A bit 2 RW Hi-Z PINA1 Input Pins, Port A bit 1 RW Hi-Z PINA0 Input Pins, Port A bit 0 RW Hi-Z [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register $05 $25 io_port.bmp N PORTB7 Port B Data Register bit 7 RW 0 PORTB6 Port B Data Register bit 6 RW 0 PORTB5 Port B Data Register bit 5 RW 0 PORTB4 Port B Data Register bit 4 RW 0 PORTB3 Port B Data Register bit 3 RW 0 PORTB2 Port B Data Register bit 2 RW 0 PORTB1 Port B Data Register bit 1 RW 0 PORTB0 Port B Data Register bit 0 RW 0 DDRB Port B Data Direction Register $04 $24 io_flag.bmp N DDB7 Port B Data Direction Register bit 7 RW 0 DDB6 Port B Data Direction Register bit 6 RW 0 DDB5 Port B Data Direction Register bit 5 RW 0 DDB4 Port B Data Direction Register bit 4 RW 0 DDB3 Port B Data Direction Register bit 3 RW 0 DDB2 Port B Data Direction Register bit 2 RW 0 DDB1 Port B Data Direction Register bit 1 RW 0 DDB0 Port B Data Direction Register bit 0 RW 0 PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. $03 $23 io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [LINCR:LINSIR:LINENIR:LINERR:LINBTR:LINBRRL:LINBRRH:LINDLR:LINIDR:LINSEL:LINDAT] io_com.bmp LIN or UART Interface LINCR LIN Control Register NA $C8 io_analo.bmp Y LSWRES Software Reset RW 0 LIN13 LIN Standard RW 0 LCONF1 LIN Configuration bit 1 RW 0 LCONF0 LIN Configuration bit 0 RW 0 LENA LIN or UART Enable RW 0 LCMD2 LIN Command and Mode bit 2 RW 0 LCMD1 LIN Command and Mode bit 1 RW 0 LCMD0 LIN Command and Mode bit 0 RW 0 LINSIR LIN Status and Interrupt Register NA $C9 io_flag.bmp Y LIDST2 Identifier Status bit 2 R 0 LIDST1 Identifier Status bit 1 R 0 LIDST0 Identifier Status bit 0 R 0 LBUSY Busy Signal R 0 LERR Error Interrupt RW 0 LIDOK Identifier Interrupt RW 0 LTXOK Transmit Performed Interrupt RW 0 LRXOK Receive Performed Interrupt RW 0 LINENIR LIN Enable Interrupt Register NA $CA io_analo.bmp Y LENERR Enable Error Interrupt RW 0 LENIDOK Enable Identifier Interrupt RW 0 LENTXOK Enable Transmit Performed Interrupt RW 0 LENRXOK Enable Receive Performed Interrupt RW 0 LINERR LIN Error Register NA $CB io_flag.bmp Y LABORT Abort Flag R 0 LTOERR Frame Time Out Error Flag R 0 LOVERR Overrun Error Flag R 0 LFERR Framing Error Flag R 0 LSERR Synchronization Error Flag R 0 LPERR Parity Error Flag R 0 LCERR Checksum Error Flag R 0 LBERR Bit Error Flag R 0 LINBTR LIN Bit Timing Register NA $CC io_flag.bmp Y LDISR Disable Bit Timing Resynchronization RW 0 LBT5 LIN Bit Timing bit 5 RW 1 LBT4 LIN Bit Timing bit 4 RW 0 LBT3 LIN Bit Timing bit 3 RW 0 LBT2 LIN Bit Timing bit 2 RW 0 LBT1 LIN Bit Timing bit 1 RW 0 LBT0 LIN Bit Timing bit 0 RW 0 LINBRRL LIN Baud Rate Low Register NA $CD io_timer.bmp Y LDIV7 RW 0 LDIV6 RW 0 LDIV5 RW 0 LDIV4 RW 0 LDIV3 RW 0 LDIV2 RW 0 LDIV1 RW 0 LDIV0 RW 0 LINBRRH LIN Baud Rate High Register NA $CE io_timer.bmp Y LDIV11 RW 0 LDIV10 RW 0 LDIV9 RW 0 LDIV8 RW 0 LINDLR LIN Data Length Register NA $CF io_com.bmp Y LTXDL3 LIN Transmit Data Length bit 3 RW 0 LTXDL2 LIN Transmit Data Length bit 2 RW 0 LTXDL1 LIN Transmit Data Length bit 1 RW 0 LTXDL0 LIN Transmit Data Length bit 0 RW 0 LRXDL3 LIN Receive Data Length bit 3 RW 0 LRXDL2 LIN Receive Data Length bit 2 RW 0 LRXDL1 LIN Receive Data Length bit 1 RW 0 LRXDL0 LIN Receive Data Length bit 0 RW 0 LINIDR LIN Identifier Register NA $D0 io_com.bmp Y LP1 Parity bit 1 R 0 LP0 Parity bit 0 R 0 LID5 Identifier bit 5 or Data Length bit 1 RW 0 LID4 Identifier bit 4 or Data Length bit 0 RW 0 LID3 Identifier bit 3 RW 0 LID2 Identifier bit 2 RW 0 LID1 Identifier bit 1 RW 0 LID0 Identifier bit 0 RW 0 LINSEL LIN Data Buffer Selection Register NA $D1 io_com.bmp Y LAINC Auto Increment of Data Buffer Index (Active Low) RW 0 LINDX2 FIFO LIN Data Buffer Index bit 2 RW 0 LINDX1 FIFO LIN Data Buffer Index bit 1 RW 0 LINDX0 FIFO LIN Data Buffer Index bit 0 RW 0 LINDAT LIN Data Register NA $D2 io_com.bmp Y LDATA7 RW 0 LDATA6 RW 0 LDATA5 RW 0 LDATA4 RW 0 LDATA3 RW 0 LDATA2 RW 0 LDATA1 RW 0 LDATA0 RW 0 [USIPP:USIBR:USIDR:USISR:USICR] io_com.bmp Universal Serial Interface USIPP USI Pin Position NA $BC io_com.bmp N USIPOS USI Pin Position RW 0 USIBR USI Buffer Register NA $BB io_com.bmp N USIBR7 USI Buffer Register bit 7 R 0 USIBR6 USI Buffer Register bit 6 R 0 USIBR5 USI Buffer Register bit 5 R 0 USIBR4 USI Buffer Register bit 4 R 0 USIBR3 USI Buffer Register bit 3 R 0 USIBR2 USI Buffer Register bit 2 R 0 USIBR1 USI Buffer Register bit 1 R 0 USIBR0 USI Buffer Register bit 0 R 0 USIDR USI Data Register NA $BA io_com.bmp N USIDR7 USI Data Register bit 7 RW 0 USIDR6 USI Data Register bit 6 RW 0 USIDR5 USI Data Register bit 5 RW 0 USIDR4 USI Data Register bit 4 RW 0 USIDR3 USI Data Register bit 3 RW 0 USIDR2 USI Data Register bit 2 RW 0 USIDR1 USI Data Register bit 1 RW 0 USIDR0 USI Data Register bit 0 RW 0 USISR USI Status Register NA $B9 io_flag.bmp Y USISIF Start Condition Interrupt Flag RW 0 USIOIF Counter Overflow Interrupt Flag RW 0 USIPF Stop Condition Flag RW 1 USIDC Data Output Collision RW 0 USICNT3 USI Counter Value Bit 3 RW 0 USICNT2 USI Counter Value Bit 2 RW 0 USICNT1 USI Counter Value Bit 1 RW 0 USICNT0 USI Counter Value Bit 0 RW 0 USICR USI Control Register NA $B8 io_flag.bmp Y USISIE Start Condition Interrupt Enable RW 0 USIOIE Counter Overflow Interrupt Enable RW 0 USIWM1 USI Wire Mode Bit 1 RW 1 USIWM0 USI Wire Mode Bit 0 RW COMM_USI_OP 0 USICS1 USI Clock Source Select Bit 1 RW 0 USICS0 USI Clock Source Select Bit 0 RW 0 USICLK Clock Strobe R 0 USITC Toggle Clock Port Pin W 0 [TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:ASSR:GTCCR] io_timer.bmp At8pwm0_tiny167 TIMSK0 Timer/Counter0 Interrupt Mask register NA $6E io_flag.bmp Y OCIE0A Timer/Counter0 Output Compare Match A Interrupt Enable RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable RW 0 TIFR0 Timer/Counter0 Interrupt Flag Register $15 $35 io_flag.bmp Y OCF0A Output Compare Flag 0A RW 0 TOV0 Timer/Counter0 Overflow Flag RW 0 TCCR0A Timer/Counter0 Control Register A $25 $45 io_flag.bmp Y COM0A1 Compare Output Mode bit 1 RW 0 COM0A0 Compare Output Mode bit 0 RW 0 WGM01 Waveform Genration Mode bit 1 RW 0 WGM00 Waveform Genration Mode bit 0 RW 0 TCCR0B Timer/Counter0 Control Register B $26 $46 io_flag.bmp Y FOC0A Force Output Compare A RW 0 CS02 Clock Select bit 2 RW 0 CS01 Clock Select bit 1 RW 0 CS00 Clock Select bit 0 RW CLK_SEL_3BIT 0 TCNT0 Timer/Counter0 $27 $47 io_timer.bmp N TCNT07 Timer/Counter 0 bit 7 RW 0 TCNT06 Timer/Counter 0 bit 6 RW 0 TCNT05 Timer/Counter 0 bit 5 RW 0 TCNT04 Timer/Counter 0 bit 4 RW 0 TCNT03 Timer/Counter 0 bit 3 RW 0 TCNT02 Timer/Counter 0 bit 2 RW 0 TCNT01 Timer/Counter 0 bit 1 RW 0 TCNT00 Timer/Counter 0 bit 0 RW 0 OCR0A Timer/Counter0 Output Compare Register A 0 $28 $48 io_timer.bmp N OCR07 Timer/Counter0 Output Compare Register Bit 7 RW 0 OCR06 Timer/Counter0 Output Compare Register Bit 6 RW 0 OCR05 Timer/Counter0 Output Compare Register Bit 5 RW 0 OCR04 Timer/Counter0 Output Compare Register Bit 4 RW 0 OCR03 Timer/Counter0 Output Compare Register Bit 3 RW 0 OCR02 Timer/Counter0 Output Compare Register Bit 2 RW 0 OCR01 Timer/Counter0 Output Compare Register Bit 1 RW 0 OCR00 Timer/Counter0 Output Compare Register Bit 0 RW 0 ASSR Asynchronous Status Register NA $B6 io_flag.bmp Y EXCLK Enable External Clock Input RW 0 AS0 Asynchronous Timer/Counter0 RW 0 TCN0UB Timer/Counter0 Update Busy R 0 OCR0AUB Output Compare Register 0A Update Busy R 0 TCR0AUB Timer/Counter0 Control Register A Update Busy R 0 TCR0BUB Timer/Counter0 Control Register B Update Busy R 0 GTCCR General Timer Counter Control register $23 $43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode RW 0 PSR0 Prescaler Reset Asynchronous 8-bit Timer/Counter0 RW 0 PSR1 Prescaler Reset Synchronous 16-bit Timer/Counter1 RW 0 [TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCCR1D:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L] io_timer.bmp t16pwm1_tiny167.xml TIMSK1 Timer/Counter1 Interrupt Mask Register NA $6F io_flag.bmp Y ICIE1 Timer/Counter1 Input Capture Interrupt Enable RW 0 OCIE1B Timer/Counter1 Output Compare B Match Interrupt Enable RW 0 OCIE1A Timer/Counter1 Output Compare A Match Interrupt Enable RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable RW 0 TIFR1 Timer/Counter1 Interrupt Flag register $16 $36 io_flag.bmp Y ICF1 Timer/Counter1 Input Capture Flag RW 0 OCF1B Timer/Counter1 Output Compare B Match Flag RW 0 OCF1A Timer/Counter1 Output Compare A Match Flag RW 0 TOV1 Timer/Counter1 Overflow Flag RW 0 TCCR1A Timer/Counter1 Control Register A NA $80 io_flag.bmp Y COM1A1 Compare Output Mode 1A, bit 1 RW 0 COM1A0 Comparet Ouput Mode 1A, bit 0 RW 0 COM1B1 Compare Output Mode 1B, bit 1 RW 0 COM1B0 Comparet Ouput Mode 1B, bit 0 RW 0 WGM11 PWM11 Pulse Width Modulator Select Bit 1 RW 0 WGM10 PWM10 Pulse Width Modulator Select Bit 0 RW 0 TCCR1B Timer/Counter1 Control Register B NA $81 io_flag.bmp Y ICNC1 Input Capture 1 Noise Canceler RW 0 ICES1 Input Capture 1 Edge Select RW 0 WGM13 Waveform Generation Mode Bit 3 RW 0 WGM12 Waveform Generation Mode Bit 2 RW 0 CS12 Timer/Counter1 Clock Select bit 2 RW 0 CS11 Timer/Counter1 Clock Select bit 1 RW 0 CS10 Timer/Counter1 Clock Select bit 0 RW CLK_SEL_3BIT_EXT 0 TCCR1C Timer/Counter1 Control Register C NA $82 io_port.bmp Y FOC1A Timer/Counter1 Force Output Compare for Channel A RW 0 FOC1B Timer/Counter1 Force Output Compare for Channel B RW 0 TCCR1D Timer/Counter1 Control Register D NA $83 io_flag.bmp Y OC1BX Timer/Counter1 Output Compare X-pin Enable for Channel B RW 0 OC1BW Timer/Counter1 Output Compare W-pin Enable for Channel B RW 0 OC1BV Timer/Counter1 Output Compare V-pin Enable for Channel B RW 0 OC1BU Timer/Counter1 Output Compare U-pin Enable for Channel B RW 0 OC1AX Timer/Counter1 Output Compare X-pin Enable for Channel A RW 0 OC1AW Timer/Counter1 Output Compare W-pin Enable for Channel A RW 0 OC1AV Timer/Counter1 Output Compare V-pin Enable for Channel A RW 0 OC1AU Timer/Counter1 Output Compare U-pin Enable for Channel A RW 0 TCNT1H Timer/Counter1 High Byte NA $85 io_timer.bmp N TCNT1H7 Timer/Counter1 High Byte bit 7 RW 0 TCNT1H6 Timer/Counter1 High Byte bit 6 RW 0 TCNT1H5 Timer/Counter1 High Byte bit 5 RW 0 TCNT1H4 Timer/Counter1 High Byte bit 4 RW 0 TCNT1H3 Timer/Counter1 High Byte bit 3 RW 0 TCNT1H2 Timer/Counter1 High Byte bit 2 RW 0 TCNT1H1 Timer/Counter1 High Byte bit 1 RW 0 TCNT1H0 Timer/Counter1 High Byte bit 0 RW 0 TCNT1L Timer/Counter1 Low Byte NA $84 io_timer.bmp N TCNT1L7 Timer/Counter1 Low Byte bit 7 RW 0 TCNT1L6 Timer/Counter1 Low Byte bit 6 RW 0 TCNT1L5 Timer/Counter1 Low Byte bit 5 RW 0 TCNT1L4 Timer/Counter1 Low Byte bit 4 RW 0 TCNT1L3 Timer/Counter1 Low Byte bit 3 RW 0 TCNT1L2 Timer/Counter1 Low Byte bit 2 RW 0 TCNT1L1 Timer/Counter1 Low Byte bit 1 RW 0 TCNT1L0 Timer/Counter1 Low Byte bit 0 RW 0 OCR1AH Timer/Counter1 Output Compare Register A High Byte NA $89 io_timer.bmp N OCR1AH7 Timer/Counter1 Output Compare Register A High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Output Compare Register A High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Output Compare Register A High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Output Compare Register A High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Output Compare Register A High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Output Compare Register A High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Output Compare Register A High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Output Compare Register A High Byte bit 0 RW 0 OCR1AL Timer/Counter1 Output Compare Register A Low Byte NA $88 io_timer.bmp N OCR1AL7 Timer/Counter1 Output Compare Register A Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Output Compare Register A Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Output Compare Register A Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Output Compare Register A Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Output Compare Register A Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Output Compare Register A Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Output Compare Register A Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Output Compare Register A Low Byte Bit 0 RW 0 OCR1BH Timer/Counter1 Output Compare Register B High Byte NA $8B io_timer.bmp N OCR1BH7 Timer/Counter1 Output Compare Register B High Byte bit 7 RW 0 OCR1BH6 Timer/Counter1 Output Compare Register B High Byte bit 6 RW 0 OCR1BH5 Timer/Counter1 Output Compare Register B High Byte bit 5 RW 0 OCR1BH4 Timer/Counter1 Output Compare Register B High Byte bit 4 RW 0 OCR1BH3 Timer/Counter1 Output Compare Register B High Byte bit 3 RW 0 OCR1BH2 Timer/Counter1 Output Compare Register B High Byte bit 2 RW 0 OCR1BH1 Timer/Counter1 Output Compare Register B High Byte bit 1 RW 0 OCR1BH0 Timer/Counter1 Output Compare Register B High Byte bit 0 RW 0 OCR1BL Timer/Counter1 Output Compare Register B Low Byte NA $8A io_timer.bmp N OCR1BL7 Timer/Counter1 Output Compare Register B Low Byte Bit 7 RW 0 OCR1BL6 Timer/Counter1 Output Compare Register B Low Byte Bit 6 RW 0 OCR1BL5 Timer/Counter1 Output Compare Register B Low Byte Bit 5 RW 0 OCR1BL4 Timer/Counter1 Output Compare Register B Low Byte Bit 4 RW 0 OCR1BL3 Timer/Counter1 Output Compare Register B Low Byte Bit 3 RW 0 OCR1BL2 Timer/Counter1 Output Compare Register B Low Byte Bit 2 RW 0 OCR1BL1 Timer/Counter1 Output Compare Register B Low Byte Bit 1 RW 0 OCR1BL0 Timer/Counter1 Output Compare Register B Low Byte Bit 0 RW 0 ICR1H Timer/Counter1 Input Capture Register High Byte NA $87 io_timer.bmp N ICR1H7 Timer/Counter1 Input Capture Register High Byte bit 7 RW 0 ICR1H6 Timer/Counter1 Input Capture Register High Byte bit 6 R 0 ICR1H5 Timer/Counter1 Input Capture Register High Byte bit 5 R 0 ICR1H4 Timer/Counter1 Input Capture Register High Byte bit 4 R 0 ICR1H3 Timer/Counter1 Input Capture Register High Byte bit 3 R 0 ICR1H2 Timer/Counter1 Input Capture Register High Byte bit 2 R 0 ICR1H1 Timer/Counter1 Input Capture Register High Byte bit 1 R 0 ICR1H0 Timer/Counter1 Input Capture Register High Byte bit 0 R 0 ICR1L Timer/Counter1 Input Capture Register Low Byte NA $86 io_timer.bmp N ICR1L7 Timer/Counter1 Input Capture Register Low Byte bit 7 R 0 ICR1L6 Timer/Counter1 Input Capture Register Low Byte bit 6 R 0 ICR1L5 Timer/Counter1 Input Capture Register Low Byte bit 5 R 0 ICR1L4 Timer/Counter1 Input Capture Register Low Byte bit 4 R 0 ICR1L3 Timer/Counter1 Input Capture Register Low Byte bit 3 R 0 ICR1L2 Timer/Counter1 Input Capture Register Low Byte bit 2 R 0 ICR1L1 Timer/Counter1 Input Capture Register Low Byte bit 1 R 0 ICR1L0 Timer/Counter1 Input Capture Register Low Byte bit 0 R 0 [WDTCR] io_watch.bmp WDTCR WDTCSR Watchdog Timer Control Register NA $60 io_flag.bmp Y WDIF Watchdog Timeout Interrupt Flag RW 0 WDIE Watchdog Timeout Interrupt Enable RW 0 WDP3 Watchdog Timer Prescaler Bit 3 WDOG_TIMER_PRESCALE_4BITS RW 0 WDCE WDTOE Watchdog Change Enable RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [EEARL:EEARH:EEDR:EECR] io_cpu.bmp EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execut EEARH EEPROM Address Register High Byte $22 $42 io_cpu.bmp N EEAR8 EEPROM Read/Write Access Bit 0 RW 0 EEARL EEPROM Address Register Low Byte $21 $41 io_cpu.bmp N EEAR7 EEPROM Read/Write Access Bit 7 RW 0 EEAR6 EEPROM Read/Write Access Bit 6 RW 0 EEAR5 EEPROM Read/Write Access Bit 5 RW 0 EEAR4 EEPROM Read/Write Access Bit 4 RW 0 EEAR3 EEPROM Read/Write Access Bit 3 RW 0 EEAR2 EEPROM Read/Write Access Bit 2 RW 0 EEAR1 EEPROM Read/Write Access Bit 1 RW 0 EEAR0 EEPROM Read/Write Access Bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $20 $40 io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register $1F $3F io_flag.bmp Y EEPM1 EEPROM Programming Mode Bit 1 The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. RW X EEPM0 EEPROM Programming Mode Bit 0 The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. RW EEP_MODE X EERIE EEPROM Ready Interrupt Enable EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. RW 0 EEMPE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. RW 0 EEPE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed RW X EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU RW 0 [SPDR:SPSR:SPCR] io_com.bmp SPI_01 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode SPDR SPI Data Register The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. $2E $4E io_com.bmp N SPDR7 SPI Data Register bit 7 RW X SPDR6 SPI Data Register bit 6 RW X SPDR5 SPI Data Register bit 5 RW X SPDR4 SPI Data Register bit 4 RW X SPDR3 SPI Data Register bit 3 RW X SPDR2 SPI Data Register bit 2 RW X SPDR1 SPI Data Register bit 1 R 0 SPDR0 SPI Data Register bit 0 R 0 SPSR SPI Status Register $2D $4D io_flag.bmp Y SPIF SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR). R 0 WCOL Write Collision Flag The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. R 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification. RW 0 SPCR SPI Control Register $2C $4C io_flag.bmp Y SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled. RW 0 SPE SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. RW 0 DORD Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. RW 0 MSTR Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. RW 0 CPOL Clock polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information. RW 0 CPHA Clock Phase Refer to Figure 36 or Figure 37 for the functionality of this bit. RW 0 SPR1 SPI Clock Rate Select 1 RW 0 SPR0 SPI Clock Rate Select 0 RW COMM_SCK_RATE_3BIT 0 [ADMUX:ADCSRA:ADCSRB:ADCH:ADCL:AMISCR:DIDR1:DIDR0] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD Converter Feature list: 10-bit Resolution. 1.0 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. 260 µs Conversion Time up to TBD 13 µs. 11 Multiplexed Single Ended Input Channels. 8 Differential input channels. ADMUX The ADC multiplexer Selection Register NA $7C io_analo.bmp Y REFS1 Reference Selection Bit 1 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 REFS0 Reference Selection Bit 0 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW ANALOG_ADC_V_REF8 0 ADLAR Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW 0 MUX4 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. RW 0 MUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. RW 0 MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju NA $79 io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad NA $78 io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 ADCSRA The ADC Control and Status register A NA $7A io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADATE ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW ANALIG_ADC_PRESCALER 0 ADCSRB The ADC Control and Status register B (Shared with ANALOG_COMPARATOR IO_MODULE) NA $7B io_flag.bmp Y BIN Bipolar Input Mode In the bipolar mode the resolution is 9 bits +1 sign bit and in the unipolar mode the resolution is 10 bits. RW 0 ADTS2 ADC Auto Trigger Source bit 2 Please refer to table in datasheet for trigger selection. RW 0 ADTS1 ADC Auto Trigger Source bit 1 Please refer to table in datasheet for trigger selection. RW 0 ADTS0 ADC Auto Trigger Source bit 0 Please refer to table in datasheet for trigger selection. RW ANALIG_ADC_AUTO_TRIGGER4 0 AMISCR Analog Miscellaneous Control Register (Shared with CURRENT_SOURCE IO_MODULE) Control of External Voltage Reference Input and Internal Voltage Reference Output. NA $77 io_analo.bmp Y AREFEN External Voltage Reference Input Enable RW 0 XREFEN Internal Voltage Reference Output Enable RW 0 DIDR1 Digital Input Disable Register 1 When a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. NA $7F io_analo.bmp Y ADC10D RW 0 ADC9D RW 0 ADC8D RW 0 DIDR0 Digital Input Disable Register 0 When a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. NA $7E io_analo.bmp Y ADC7D AIN1D RW 0 ADC6D AIN0D RW 0 ADC5D RW 0 ADC4D RW 0 ADC3D RW 0 ADC2D RW 0 ADC1D RW 0 ADC0D RW 0 [AMISCR] io_analo.bmp 100 µA Constant current source. +- 2% Absolute Accuracy. AMISCR Analog Miscellaneous Control Register (Shared with AD_CONVERTER IO_MODULE) Control of Current Source Output. NA $77 io_analo.bmp Y ISRCEN Current Source Enable RW 0 [ADCSRB:ACSR] io_analo.bmp AlgComp_tiny167 ADCSRB Analog Comparator & ADC Control and Status Register B (Shared with AD_CONVERTER IO_MODULE) NA $7B io_flag.bmp Y ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the positive input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the positive input of the Analog Comparator. RW 0 ACIR1 Analog Comparator Internal Voltage Reference Select Bit 1 Refer to Analog Comparator Negative Input table. RW 0 ACIR0 Analog Comparator Internal Voltage Reference Select Bit 0 Refer to Analog Comparator Negative Input table. RW 0 ACSR Analog Comparator Control And Status Register $30 $50 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. RW 0 ACIRS Analog Comparator Internal Reference Select When this bit is set an Internal Reference Voltage replaces the negative input to the Analog Comparator (c.f. Analog Comparator Negative Input table). If ACIRS is cleared, AIN0 is applied to the negative input to the Analog Comparator. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIC Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. R 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW ANALOG_COMP_INTERRUPT 0 [EICRA:EIMSK:EIFR:PCICR:PCIFR:PCMSK1:PCMSK0] io_ext.bmp The External Interrupts are triggered by the INT1..0 pins or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT1..0 or PCINT15..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. EICRA External Interrupt Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. NA $69 io_flag.bmp Y ISC11 External Interrupt Sense Control 1 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set. The value on the INT1 pin is sampled before detecting edges. RW 0 ISC10 External Interrupt Sense Control 1 Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set. The value on the INT1 pin is sampled before detecting edges. RW INTERRUPT_SENSE_CONTROL2 0 ISC01 External Interrupt Sense Control 0 Bit 1 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The value on the INT0 pin is sampled before detecting edges. RW 0 ISC00 External Interrupt Sense Control 0 Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The value on the INT0 pin is sampled before detecting edges. RW INTERRUPT_SENSE_CONTROL2 0 EIMSK External Interrupt Mask Register $1D $3D io_flag.bmp Y INT1 External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. RW 0 INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. RW 0 EIFR External Interrupt Flag Register $1C $3C io_flag.bmp Y INTF1 External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). RW 0 INTF0 External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). RW 0 PCICR Pin Change Interrupt Control Register NA $68 io_cpu.bmp Y PCIE1 Pin Change Interrupt Enable on any PCINT14..8 pin When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. RW 0 PCIE0 Pin Change Interrupt Enable on any PCINT7..0 pin When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. RW 0 PCIFR Pin Change Interrupt Flag Register $1B $3B io_flag.bmp Y PCIF1 Pin Change Interrupt Flag 1 When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one) RW 0 PCIF0 Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). RW 0 PCMSK1 Pin Change Mask Register 1 Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. NA $6C io_flag.bmp Y PCINT15 Pin Change Enable Mask 15 RW 0 PCINT14 Pin Change Enable Mask 14 RW 0 PCINT13 Pin Change Enable Mask 13 RW 0 PCINT12 Pin Change Enable Mask 12 RW 0 PCINT11 Pin Change Enable Mask 11 RW 0 PCINT10 Pin Change Enable Mask 10 RW 0 PCINT9 Pin Change Enable Mask 9 RW 0 PCINT8 Pin Change Enable Mask 8 RW 0 PCMSK0 Pin Change Mask Register 0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. NA $6B io_flag.bmp Y PCINT7 Pin Change Enable Mask 7 RW 0 PCINT6 Pin Change Enable Mask 6 RW 0 PCINT5 Pin Change Enable Mask 5 RW 0 PCINT4 Pin Change Enable Mask 4 RW 0 PCINT3 Pin Change Enable Mask 3 RW 0 PCINT2 Pin Change Enable Mask 2 RW 0 PCINT1 Pin Change Enable Mask 1 RW 0 PCINT0 Pin Change Enable Mask 0 RW 0 [SPMCSR] io_cpu.bmp AVRSimIOSPM.SimIOSPM The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface (i.e. LIN, USART, ...) and associated protocol to read code and write (program) that code into the Program memory. SPMCSR Store Program Memory Control Register The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. $37 $57 io_flag.bmp Y RWWSB Read While Write Section Busy This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero in ATtiny47/87/167. R 0 SIGRD Signature Row Read If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. See “Reading the Signature Row from Software” paragraph in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. RW 0 CTPB Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. RW 0 RFLB Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation. RW 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either SIGRD, CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed RW 0 [SREG:SPH:SPL:MCUCR:MCUSR:SMCR:PRR:OSCCAL:CLKPR:CLKSELR:CLKCSR:DWDR:GPIOR2:GPIOR1:GPIOR0:PORTCR] [SPH:SPL] io_cpu.bmp SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 PRR Power Reduction Register NA $64 io_sreg.bmp Y PRLIN Power Reduction LINUART Writing a logic one to this bit shuts down the LINUART module. RW 0 PRSPI Power Reduction SPI Writing a logic one to this bit shuts down theSPI module. RW 0 PRTIM1 Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. RW 0 PRTIM0 Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. RW 0 PRUSI Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. RW 0 PRADC Power Reduction ADC Writing a logic one to this bit shuts down the ADC, Analog Comparator & Current Source. RW 0 SPH Stack Pointer High Byte $3E $5E io_sreg.bmp N SP10 Stack Pointer Bit 10 RW 0 SP9 Stack Pointer Bit 9 RW 0 SP8 Stack Pointer Bit 8 RW 0 SPL Stack Pointer Low Byte $3D $5D io_sreg.bmp N SP7 Stack Pointer Bit 7 RW 0 SP6 Stack Pointer Bit 6 RW 0 SP5 Stack Pointer Bit 5 RW 0 SP4 Stack Pointer Bit 4 RW 0 SP3 Stack Pointer Bit 3 RW 0 SP2 Stack Pointer Bit 2 RW 0 SP1 Stack Pointer Bit 1 RW 0 SP0 Stack Pointer Bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. $35 $55 io_cpu.bmp Y BODSE BOD Sleep Enable RW 0 BODS BOD Sleep RW 0 PUD Pull-up Disable RW 0 MCUSR MCU Status register The MCU Status Register provides information on which reset source caused a MCU reset. $34 $54 io_cpu.bmp Y WDRF Watchdog Reset Flag RW 0 BORF Brown-out Reset Flag RW 0 EXTRF External Reset Flag After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged. RW 0 PORF Power-On Reset Flag This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged RW 0 MCUSR Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. $33 $53 io_cpu.bmp Y SM1 Sleep Mode Select Bit 1 RW 0 SM0 Sleep Mode Select Bit 0 RW CPU_SLEEP_MODE2 0 SE Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction. R 0 OSCCAL Oscillator Calibration Register NA $66 io_sreg.bmp N CAL7 Oscillatro Calibration Value Bit 7 RW 0 CAL6 Oscillatro Calibration Value Bit 6 RW 0 CAL5 Oscillatro Calibration Value Bit 5 RW 0 CAL4 Oscillatro Calibration Value Bit 4 RW 0 CAL3 Oscillatro Calibration Value Bit 3 RW 0 CAL2 Oscillatro Calibration Value Bit 2 RW 0 CAL1 Oscillatro Calibration Value Bit 1 RW 0 CAL0 Oscillatro Calibration Value Bit 0 RW 0 CLKPR Clock Prescale Register The system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. NA $61 io_sreg.bmp Y CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only update when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS is written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. RW 0 CLKPS3 Clock Prescaler Select Bit 3 RW 0 CLKPS2 Clock Prescaler Select Bit 2 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted RW 0 CLKPS1 Clock Prescaler Select Bit 1 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted RW 0 CLKPS0 Clock Prescaler Select Bit 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted RW CPU_CLK_PRESCALE_4_BITS_SMALL 0 CLKSELR Clock Selection Register The content of this register can operate as well as the Low Fuse Byte. CKSEL3..0, SUT1..0 and CKOUT fuses are substituted as shown in Figure 4-5 on page 33 and replaced respectively by CSEL3..0, CSUT1:0 and COUT. During reset, bits of the Low Fuse Byte are latched in the CLKSELR register. NA $63 io_sreg.bmp Y COUT Clock Out - CKOUT fuse substitution RW 0 CSUT1 Clock Start-up Time bit 1 - SUT1 fuse substitution RW 0 CSUT0 Clock Start-up Time bit 0 - SUT0 fuse substitution RW 0 CSEL3 Clock Source Select bit 3 - CKSEL3 fuse substitution RW 0 CSEL2 Clock Source Select bit 2 - CKSEL2 fuse substitution RW 0 CSEL1 Clock Source Select bit 1 - CKSEL1 fuse substitution RW 0 CSEL0 Clock Source Select bit 0 - CKSEL0 fuse substitution RW 0 CLKCSR Clock Control & Status Register This register controls the dynamic clock switch circuit. NA $62 io_sreg.bmp Y CLKCCE Clock Control Change Enable The CLKCCE bit must be written to logic one to enable change of CLKCSR bits. The CLKCCE bit is only update when the other bits in CLKCSR are simultaniosly written to zero. CLKCCE is cleared by hardware four cycles after it is written or when CLKCSR is written. Rewriting the CLKCCE bit within this time-out period does neither extend the time-out period, nor clear the CLKCCE bit. RW 0 CLKRDY Clock Ready Flag R 0 CLKC3 Clock Control bit 3 RW 0 CLKC2 Clock Control bit 2 RW 0 CLKC1 Clock Control bit 1 RW 0 CLKC0 Clock Control bit 0 RW CPU_CLK_COMMAND_LIST_4_BITS 0 DWDR DebugWire data register $31 $51 io_cpu.bmp N DWDR7 RW 0 DWDR6 RW 0 DWDR5 RW 0 DWDR4 RW 0 DWDR3 RW 0 DWDR2 RW 0 DWDR1 RW 0 DWDR0 RW 0 GPIOR2 General Purpose IO register 2 $2B $4B io_sreg.bmp N GPIOR27 RW 0 GPIOR26 RW 0 GPIOR25 RW 0 GPIOR24 RW 0 GPIOR23 RW 0 GPIOR22 RW 0 GPIOR21 RW 0 GPIOR20 GPIOR27 0 GPIOR1 General Purpose register 1 $2A $4A io_sreg.bmp N GPIOR17 RW 0 GPIOR16 RW 0 GPIOR15 RW 0 GPIOR14 RW 0 GPIOR13 RW 0 GPIOR12 RW 0 GPIOR11 RW 0 GPIOR10 RW 0 GPIOR0 General purpose register 0 $1E $3E io_sreg.bmp N GPIOR07 RW 0 GPIOR06 RW 0 GPIOR05 RW 0 GPIOR04 RW 9 GPIOR03 RW 0 GPIOR02 RW 0 GPIOR01 RW 0 GPIOR00 RW 0 PORTCR General purpose register 0 $12 $32 io_port.bmp N BBMB Break-Before-Make Mode Enable Port B When these bits are written to one, the port-wise Break-Before-Make mode is activated. The intermediate tri-state cycle is then inserted when writing DDRBn to make an output. RW 0 BBMA Break-Before-Make Mode Enable Port A When these bits are written to one, the port-wise Break-Before-Make mode is activated. The intermediate tri-state cycle is then inserted when writing DDRAn to make an output. RW 0 PUDB Port-Wise Pull-up Disable Port B When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled even if the DDRBn and PORTBn Registers are configured to enable the pull-ups ({DDRBn, PORTBn} = 0, 1). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD) from the MCUCR register. RW 0 PUDA Port-Wise Pull-up Disable Port A When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled even if the DDRAn and PORTAn Registers are configured to enable the pull-ups ({DDRAn, PORTAn} = 0, 1). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD) from the MCUCR register. RW 0 [JTAGICEmkII:STK600:AVRISPmkII:AVRDragon:STK500_2:SIMULATOR:AVRONE] 0x9487 DebugWire 0x3F,0x00,0x64,0xF8,0xEF,0x3D,0xB9,0xE0 0x36,0x00,0x04,0xE0,0xEF,0x1D,0xB8,0xE0 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x5F,0xDB,0x80,0xDF,0xFF,0x0F,0x00,0x00,0x00,0x00,0x40,0x1F,0x00,0xFF,0x07,0x00 0x1C,0xDB,0x80,0xD8,0xFF,0x0F,0x00,0x00,0x00,0x00,0x40,0x15,0x00,0xF7,0x07,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00 0x57 0x0080 0x0004 0 0x00D2 0x0000,32 0x0020,64 0x00 0x40 0x00 0xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF 0xB6,0x01,0x11 0x31 0x00 0 0 0x00 0x00 0x00 0x00 0x3F 1 0 0 1 200 100 25 32 0 3 0x53 1 1 10 0 0x41 64 10 0x40 0x4C 0x00 0x00 0x00 0x41 4 10 0xC1 0xC2 0x00 0x00 0x00 256 256 4 4 4 4 0x0E 0x1E 0x0E 0x1E 0x2E 0x3E 0x2E 0x3E 0x4E 0x5E 0x4E 0x5E 0x6E 0x7E 0x6E 0x7E 0x06 0x16 0x46 0x56 0x0A 0x1A 0x4A 0x5A 0x1E 0x7C 0x00 0x01 0x00 0x00 0x00 0x00 100 0 5 1 20 1 0 15 15 0 10 5 0x0B 256 256 5 0x05 256 256 0 5 0 5 200 100 25 32 0 3 0x53 1 1 10 0 0x41 64 10 0x40 0x4C 0x00 0x00 0x00 0x41 4 10 0xC1 0xC2 0x00 0x00 0x00 256 256 4 4 4 4 0x0E 0x1E 0x0E 0x1E 0x2E 0x3E 0x2E 0x3E 0x4E 0x5E 0x4E 0x5E 0x6E 0x7E 0x6E 0x7E 0x06 0x16 0x46 0x56 0x0A 0x1A 0x4A 0x5A 0x1E 0x7C 0x00 0x01 0x00 0x00 0x00 0x00 100 0 5 1 15 1 0 15 15 0 10 5 0x0D 256 256 5 0x05 256 256 0 5 0 5 AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x20 0 14 AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOExtInterrupt.SimIOExtInterrupt 0x02 0x1D 0x01 0x1C 0x01 0x03 0x40 0x49 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x04 0x1D 0x02 0x1C 0x02 0x00 0x08 0x49 0x0C AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x06 0x48 0x01 0x1B 0x01 0x00 0xff 0x4B AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x08 0x48 0x02 0x1B 0x02 0x03 0xff 0x4C AvrMasterTimer.MasterTimer 0x14 0x16 PORTA 2 1:8:32:64:128:256:1024 AVRSimIOTimert16pwm1.SimIOTimert16pwm1 0x0C 0x0E 0x10 0x12 0x00 0x20 0x00 0x10 0x05 0x55 0x05 0xAA AvrMasterTimer.MasterTimer 128 1 0x0A 2048:4096:8192:16384:32768:65536:131072:262144:524288:1048576 AVRSimAC.SimIOAC 0x22 AvrSimADC.SimADC 0x1E AvrSimUSI.SimUSI 0x24 0x26 AVRSimIOSpi.SimIOSpi 0x1C 0x00 0x20 0x00 0x04 0x00 0x10 0x00 0x01 0x40 0xFF 0xFF 0xFF 0xFF 0x9487 DebugWire