[ADMIN:CORE:INTERRUPT_VECTOR:MEMORY:PACKAGE:FUSE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS] ATtiny15 1.6MHZ 214 RELEASED $1E $90 $06 V0E AVRSimCoreV0.SimCoreV0 [] [] [] 32 $00 $1B $1A $1D $1C $1F $1E 9 $000 RESET External Reset, Power-on Reset and Watchdog Reset $001 INT0 External Interrupt 0 $002 I/O_PINS External Interrupt Request 0 $003 TIMER1_COMP Timer/Counter1 Compare Match $004 TIMER1_OVF Timer/Counter1 Overflow $005 TIMER0_OVF Timer/Counter0 Overflow $006 EE_RDY EEPROM Ready $007 ANA_COMP Analog Comparator $008 ADC ADC Conversion Ready AVRSimMemory8bit.SimMemory8bit 1024 64 0 NA 0 NA $00 $3F NA NA $20 $5F $3F NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3B NA 0x20 0x40 $3A NA 0x20 0x40 $39 NA 0x02 0x04 0x40 $38 NA 0x02 0x04 0x40 $35 NA 0x01 0x02 0x08 0x10 0x20 0x40 $34 NA 0x01 0x02 0x04 0x08 $33 NA 0x01 0x02 0x04 $32 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $31 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $30 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2F NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2E NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2D NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2C NA 0x01 0x02 0x04 $21 NA 0x01 0x02 0x04 0x08 0x10 $1E NA 0x01 0x02 0x04 0x08 0x10 0x20 $1D NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1C NA 0x01 0x02 0x04 0x08 $18 NA $1f 0x01 0x02 0x04 0x08 0x10 $17 NA $3f 0x01 0x02 0x04 0x08 0x10 0x20 $16 NA $3f 0x01 0x02 0x04 0x08 0x10 0x20 $08 NA 0x01 0x02 0x08 0x10 0x20 0x40 0x80 $07 NA 0x01 0x02 0x04 0x20 0x40 0x80 $06 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $05 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $04 NA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 [DIP] 8 [PB5:'RESET:ADC0] [PB4:ADC3] [PB3:ADC2] [GND] [PB0:MOSI:AIN0:AREF] [PB1:MISO:AIN1:OCP] [PB2:SCK:ADC1:T0:INT0] [VCC] [LOW] 9 6 0x80 0x80 Brown-out detection level at VCC=2.7 V 0x80 0x00 Brown-out detection level at VCC=4.0 V 0x40 0x00 Brown-out detection enabled 0x20 0x00 Serial program downloading (SPI) enabled 0x10 0x00 External reset function of PB5 disabled 0x03 0x03 CKSEL=11 Very quickly rising power 0x03 0x02 CKSEL=10 Quickly rising power 0x03 0x01 CKSEL=01 Slowly rising power 0x03 0x00 CKSEL=00 Slowly rising power 0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 0,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 0,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 0x00,1.6 MHz 0 2 [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x06 0x06 Mode 1: No memory lock features enabled 0x06 0x04 Mode 2: Further programming disabled 0x06 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit [AD_CONVERTER:ANALOG_COMPARATOR:EEPROM:PORTB:TIMER_COUNTER_0:WATCHDOG:CPU:EXTERNAL_INTERRUPT:TIMER_COUNTER_1] [ADMUX:ADCSR:ADCH:ADCL] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise ADMUX The ADC multiplexer Selection Register $07 NA io_analo.bmp Y REFS1 Reference Selection Bit 1 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 REFS0 Reference Selection Bit 0 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW ANALOG_ADC_V_REF 0 ADLAR Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW 0 MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 ADCSR The ADC Control and Status register $06 NA io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADFR ADC Free Running Select When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW ANALIG_ADC_PRESCALER 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju $05 NA io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad $04 NA io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 [ACSR] io_analo.bmp AlgComp_06 ACSR Analog Comparator Control And Status Register $08 NA io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG AINBG6 Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW ANALOG_COMP_INTERRUPT 0 [EEAR:EEDR:EECR] io_cpu.bmp EEPROM_02.xml EEAR EEPROM Read/Write Access The EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction $1E NA io_cpu.bmp N EEAR5 EEPROM Read/Write Access bit 5 RW 0 EEAR4 EEPROM Read/Write Access bit 4 RW 0 EEAR3 EEPROM Read/Write Access bit 3 RW 0 EEAR2 EEPROM Read/Write Access bit 2 RW 0 EEAR1 EEPROM Read/Write Access bit 1 RW 0 EEAR0 EEPROM Read/Write Access bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $1D NA io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register $1C NA io_flag.bmp Y EERIE EEProm Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero). RW 0 EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. RW 0 EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. RW 0 EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined. RW 0 [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Data Register, Port B $18 NA io_port.bmp N PORTB4 RW 0 PORTB3 RW 0 PORTB2 RW 0 PORTB1 RW 0 PORTB0 RW 0 DDRB Data Direction Register, Port B $17 NA io_flag.bmp N DDB5 RW 0 DDB4 RW 0 DDB3 RW 0 DDB2 RW 0 DDB1 RW 0 DDB0 RW 0 PINB Input Pins, Port B $16 NA io_port.bmp N PINB5 R 0 PINB4 R 0 PINB3 R 0 PINB2 R 0 PINB1 R 0 PINB0 R 0 [TIMSK:TIFR:TCCR0:TCNT0] io_timer.bmp t81 The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions TIMSK Timer/Counter Interrupt Mask Register $39 NA io_flag.bmp Y TOIE0 Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR Timer/Counter Interrupt Flag register $38 NA io_flag.bmp Y TOV0 Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. RW 0 TCCR0 Timer/Counter0 Control Register $33 NA io_flag.bmp Y CS02 Clock Select0 bit 2 RW CLK_SEL_3BIT_EXT 0 CS01 Clock Select0 bit 1 RW 0 CS00 Clock Select0 bit 0 RW 0 TCNT0 Timer Counter 0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. $32 NA io_timer.bmp N TCNT07 Timer Counter 0 bit 7 RW 0 TCNT06 Timer Counter 0 bit 6 RW 0 TCNT05 Timer Counter 0 bit 5 RW 0 TCNT04 Timer Counter 0 bit 4 RW 0 TCNT03 Timer Counter 0 bit 3 RW 0 TCNT02 Timer Counter 0 bit 2 RW 0 TCNT01 Timer Counter 0 bit 1 RW 0 TCNT00 Timer Counter 0 bit 0 RW 0 [WDTCR] io_watch.bmp WDTCR Watchdog Timer Control Register $21 NA io_flag.bmp Y WDTOE WDDE RW This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure. RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW WDOG_TIMER_PRESCALE_3BITS 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [SREG:MCUCR:MCUSR:OSCCAL] io_cpu.com SREG Status Register $3F NA io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. $35 NA io_cpu.bmp Y PUD Pull-up Disable RW 0 SE Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction. R 0 SM1 Sleep Mode Select Bit 1 RW 0 SM0 Sleep Mode Select Bit 0 RW CPU_SLEEP_MODE2 0 ISC01 Interrupt Sense Control 0 bit 1 R 0 ISC00 Interrupt Sense Control 0 bit 0 R INTERRUPT_SENSE_CONTROL2 0 MCUSR MCU Status register The MCU Status Registerprovides information on which reset source caused a MCU reset. $34 NA io_cpu.bmp Y WDRF Watchdog Reset Flag RW 0 BORF Brown-out Reset Flag RW 0 EXTRF External Reset Flag After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged. RW 0 PORF Power-On Reset Flag This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged RW 0 OSCCAL Status Register $31 NA io_sreg.bmp N CAL7 Oscillator Calibration Value Bit 7 RW 0 CAL6 Oscillator Calibration Value Bit 6 RW 0 CAL5 Oscillator Calibration Value Bit 5 RW 0 CAL4 Oscillator Calibration Value Bit 4 RW 0 CAL3 Oscillator Calibration Value Bit 3 RW 0 CAL2 Oscillator Calibration Value Bit 2 RW 0 CAL1 Oscillator Calibration Value Bit 1 RW 0 CAL0 Oscillator Calibration Value Bit 0 RW 0 [GIMSK:GIFR] io_ext.bmp GIMSK General Interrupt Mask Register $3B NA io_flag.bmp Y INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits RW 0 PCIE Pin Change Interrupt Enable RW 0 GIFR General Interrupt Flag register $3A NA io_flag.bmp Y INTF0 External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCIF Pin Change Interrupt Flag RW 0 [TCCR1:TCNT1:OCR1A:OCR1B:TIMSK:TIFR:SFIOR] io_timer.bmp t8pwm1_00 TCCR1 Timer/Counter Control Register $30 NA io_flag.bmp Y CTC1 Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1A register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. RW 0 PWM1 Pulse Width Modulator Enable When set (one), this bit enables PWM mode for Timer/Counter1. RW 0 COM1A1 Compare Output Mode, Bit 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin. RW 0 COM1A0 Compare Output Mode, Bit 1 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin. RW CLK_COMP_MATCH_OUT_MODE 0 CS13 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 CS12 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 CS11 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 CS10 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW CLK_SEL_4BIT_FAST 0 TCNT1 Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT1 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT1) while the counter is running, introduces a risk of missing a compare match between TCNT1 the OCR2 register. $2F NA io_timer.bmp N TCNT1_7 Timer/Counter Register Bit 7 RW 0 TCNT1_6 Timer/Counter Register Bit 6 RW 0 TCNT1_5 Timer/Counter Register Bit 5 RW 0 TCNT1_4 Timer/Counter Register Bit 4 RW 0 TCNT1_3 Timer/Counter Register Bit 3 RW 0 TCNT1_2 Timer/Counter Register Bit 2 RW 0 TCNT1_1 Timer/Counter Register Bit 1 RW 0 TCNT1_0 Timer/Counter Register Bit 0 RW 0 OCR1A Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. $2E NA io_timer.bmp N OCR1A7 Output Compare Register A Bit 7 RW 0 OCR1A6 Output Compare Register A Bit 6 RW 0 OCR1A5 Output Compare Register A Bit 5 RW 0 OCR1A4 Output Compare Register A Bit 4 RW 0 OCR1A3 Output Compare Register A Bit 3 RW 0 OCR1A2 Output Compare Register A Bit 2 RW 0 OCR1A1 Output Compare Register A Bit 1 RW 0 OCR1A0 Output Compare Register A Bit 0 RW 0 OCR1B Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. $2D NA io_timer.bmp N OCR1B7 Output Compare Register B Bit 7 RW 0 OCR1B6 Output Compare Register B Bit 6 RW 0 OCR1B5 Output Compare Register B Bit 5 RW 0 OCR1B4 Output Compare Register B Bit 4 RW 0 OCR1B3 Output Compare Register B Bit 3 RW 0 OCR1B2 Output Compare Register B Bit 2 RW 0 OCR1B1 Output Compare Register B Bit 1 RW 0 OCR1B0 Output Compare Register B Bit 0 RW 0 TIMSK Timer/Counter Interrupt Mask Register $39 NA io_flag.bmp Y OCIE1A OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match, interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR). RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]). RW 0 TIFR Timer/Counter Interrupt Flag Register $38 NA io_flag.bmp Y OCF1A Timer/Counter1 Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed. RW 0 TOV1 Timer/Counter1 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overf low Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. RW 0 SFIOR Special Function IO Register $2C NA io_flag.bmp FOC1A Force Output Compare 1A Writing a logical “1” to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and the Timer/Counter1 will not be cleared even if CTC1 is set. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM mode RW 0 PSR1 Prescaler Reset Timer/Counter1 When this bit is set (one) the Timer/Counter1 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a “0” to this bit will have no effect. This bit will always be read as zero. RW 0 PSR0 Prescaler Reset Timer/Counter0 When this bit is set (one) the Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a “0” to this bit will have no effect. This bit will always be read as zero. RW 0 [SIMULATOR:STK500:STK500_2:AVRISPmkII:AVRDragon:STK600] AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x06 0 7 AVRSimIOPort.SimIOPort 0xff N AVRSimIOExtInterrupt.SimIOExtInterrupt 0x01 0x3b 0x40 0x3a 0x40 0x16 0x04 0x35 0x03 AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x02 0x3B 0x20 0x3A 0x20 0x00 0x16 0x3F AVRSimIOTimert81.SimIOTimert81 0x05 0x16 0x04 AVRSimIOtimer8t15.SimIOtimer8t15 AVRSimAC.SimIOAC 0x07 AVRSimADC.SimADC 0x08 0x13 1 0 1 0xFF 0xFF 0xFF 0 1 200 100 25 32 0 3 0x53 1 1 100 0 0x04 128 10 0x40 0x00 0x20 0xFF 0x00 0x04 64 20 0xC0 0x00 0xA0 0xFF 0xFF 256 256 4 4 4 4 0x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x00 0x68 0x78 0x68 0x68 0x00 0x00 0x68 0x78 0x78 0x00 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x00 100 5 6 16 1 25 1 0 100 25 40 0 0 256 5 256 0 256 5 256 25 25 200 100 25 32 0 3 0x53 1 1 100 0 0x04 128 5 0x40 0x00 0x20 0xFF 0x00 0x04 64 10 0xC0 0x00 0xA0 0xFF 0xFF 256 256 4 4 4 4 0x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x00 0x68 0x78 0x68 0x68 0x00 0x00 0x68 0x78 0x78 0x00 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x00 100 5 6 16 1 20 0 50 100 25 40 0 0 64 5 256 0 256 5 256 25 25