[ADMIN:MEMORY:PACKAGE:POWER:FUSE:LOCKBIT:PROGRAMMING:CORE:IO_MODULE:ICE_SETTINGS:INTERRUPT_VECTOR] ATmega8HVA 4MHZ 1 RELEASED $1E $93 $10 1 0x31 0 0 0x00 8192 256 512 $100 NA NA $00 $3F $60 $FF $20 $FF NA 0xFE 0x01 0x02 NA 0xFD 0x01 0x02 0x04 0x08 0x10 NA 0xFC 0x01 0x02 0x04 0x08 0x10 0x20 NA 0xFB 0x01 0x02 0x04 0x08 0x10 0x20 NA 0xFA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 NA 0xF9 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xF8 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xF7 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xF6 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xF5 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xF3 0x01 0x02 0x04 0x08 0x10 NA 0xF2 0x01 0x02 0x04 0x08 0x10 NA 0xF0 0x01 0x02 0x04 0x08 NA 0xE9 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xE8 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xE6 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xE5 0x01 0x02 0x04 0x10 0x20 0x40 NA 0xE4 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xE3 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xE2 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xE1 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xE0 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xD1 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0xD0 0x01 0x02 0x04 0x08 0x10 0x20 0x80 NA 0xC8 0x01 0x02 0x80 NA 0x89 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0x88 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0x85 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0x84 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0x81 0x01 0x02 0x04 NA 0x80 0x01 0x08 0x10 0x20 0x40 0x80 NA 0x7E 0x01 0x02 NA 0x7C 0x01 0x02 0x04 0x08 NA 0x7A 0x01 0x02 0x04 0x08 NA 0x79 0x01 0x02 0x04 0x08 NA 0x78 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0x6F 0x01 0x02 0x04 0x08 NA 0x6E 0x01 0x02 0x04 0x08 NA 0x69 0x01 0x02 0x04 0x08 0x10 0x20 NA 0x66 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 0x64 0x01 0x02 0x04 0x08 0x20 NA 0x61 0x01 0x02 0x80 NA 0x60 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x3F 0x5F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x3E 0x5E 0x01 0x02 0x3D 0x5D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x37 0x57 0x01 0x02 0x04 0x08 0x10 0x20 0x35 0x55 0x10 0x20 0x34 0x54 0x01 0x02 0x04 0x08 0x10 0x33 0x53 0x01 0x02 0x04 0x08 0x31 0x51 0x2e 0x4e 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x2d 0x4d 0x01 0x40 0x80 0x2c 0x4c 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x2B 0x4B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x2A 0x4A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x29 0x49 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x28 0x48 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x27 0x47 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x26 0x46 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x25 0x45 0x01 0x02 0x04 0x24 0x44 0x01 0x08 0x10 0x20 0x40 0x80 0x23 0x43 0x01 0x80 0x21 0x41 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x20 0x40 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x1F 0x3F 0x01 0x02 0x04 0x08 0x10 0x20 0x1E 0x3E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x1D 0x3D 0x01 0x02 0x04 0x1C 0x3C 0x01 0x02 0x04 0x17 0x37 0x01 0x02 0x10 0x16 0x36 0x01 0x02 0x04 0x08 0x15 0x35 0x01 0x02 0x04 0x08 0x08 0x28 0x01 0x06 0x26 0x01 0x05 0x25 0x01 0x02 0x04 0x08 0x04 0x24 0x01 0x02 0x04 0x08 0x03 0x23 0x01 0x02 0x04 0x08 0x02 0x22 0x01 0x02 0x01 0x21 0x01 0x02 0x00 0x20 0x01 0x02 0 0 0 0 64 [TSOP;LGA] 28 [PV2] [PV1] [NV] [GND] [VFET] [CF1P] [CF1N] [CF2P] [CF2N] [VREG] [VREF] [VREFGND] [PI] [NI] [PA0] [PA1] [PA2] [PB0] [PB1] [PB2] [PB3] [GND] [VCC] [PC0] [BATT] [GND] [NC] [OC] 4MHz 70C TBD mA TBD mA TBD uA [LOW] 8 WDTON Watchdog Timer Always On 1 EESAVE EEPROM memory is preserved through chip erase 1 SPIEN Enable Serial programming and Data Downloading 0 DWEN Enable debugWIRE 1 SELFPRGEN Enable self programming 1 SUT2 Select start-up time 1 SUT1 Select start-up time 1 SUT0 Select start-up time 1 13 0x80 0x00 Watch-dog Timer always on; [WDTON=0] 0x40 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x10 0x00 Debug Wire enable; [DWEN=0] 0x08 0x00 Self Programming enable; [SELFPRGEN=0] 0x07 0x00 Start-up time 6 CK/14 CK + 4 ms; [SUT=000] 0x07 0x01 Start-up time 6 CK/14 CK + 8 ms; [SUT=001] 0x07 0x02 Start-up time 6 CK/14 CK + 16 ms; [SUT=010] 0x07 0x03 Start-up time 6 CK/14 CK + 32 ms; [SUT=011] 0x07 0x04 Start-up time 6 CK/14 CK + 64 ms; [SUT=100] 0x07 0x05 Start-up time 6 CK/14 CK + 128 ms; [SUT=101] 0x07 0x06 Start-up time 6 CK/14 CK + 256 ms; [SUT=110] 0x07 0x07 Start-up time 6 CK/14 CK + 512 ms; [SUT=111]; default value [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit 0xdf 0xdf 0,0x20,0x00,WARNING! These fuse settings will disable the ISP interface! 0,0x10,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 0x01,8 MHz 128 4 V2E AVRSimCoreV2.SimCoreV2 [] [] [] 32 $00 $1B $1A $1D $1C $1F $1E 21 $0000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset $0001 BPINT Battery Protection Interrupt $0002 VREGMON Voltage regulator monitor interrupt $0003 INT0 External Interrupt Request 0 $0004 INT1 External Interrupt Request 1 $0005 INT2 External Interrupt Request 2 $0006 WDT Watchdog Timeout Interrupt $0007 TIMER1_IC Timer 1 Input capture $0008 TIMER1_COMPA Timer 1 Compare Match A $0009 TIMER1_COMPB Timer 1 Compare Match B $000A TIMER1_OVF Timer 1 overflow $000B TIMER0_IC Timer 0 Input Capture $000C TIMER0_COMPA Timer 0 Comapre Match A $000D TIMER0_COMPB Timer 0 Compare Match B $000E TIMER0_OVF Timer 0 Overflow $000F SPI;STC SPI Serial transfer complete $0010 VADC Voltage ADC Conversion Complete $0011 CCADC_CONV Coulomb Counter ADC Conversion Complete $0012 CCADC_REG_CUR Coloumb Counter ADC Regular Current $0013 CCADC_ACC Coloumb Counter ADC Accumulator $014 EE READY EEPROM Ready [AD_CONVERTER:WATCHDOG:BANDGAP:EXTERNAL_INTERRUPT:PORTC:PORTA:FET:SPI:BOOT_LOAD:PORTB:CPU:BATTERY_PROTECTION:EEPROM:TIMER_COUNTER_1:COULOMB_COUNTER:TIMER_COUNTER_0:VOLTAGE_REGULATOR] [VADMUX:VADCH:VADCL:VADCSR] [VADCH:VADCL] io_analo.bmp 12-bit resolution Sigmal-Delta ADC with +/-1 LSB Accuracy. 512 us conversion time. VADMUX The VADC multiplexer Selection Register NA 0x7C io_analo.bmp Y VADMUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 VADMUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 VADMUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 VADMUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 VADCH VADC Data Register High Byte When VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH. NA 0x79 io_analo.bmp N VADC11 ADC Data Register High Byte Bit 3 R 0 VADC10 ADC Data Register High Byte Bit 2 R 0 VADC9 ADC Data Register High Byte Bit 1 R 0 VADC8 ADC Data Register High Byte Bit 0 R 0 VADCL VADC Data Register Low Byte When VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH. NA 0x78 io_analo.bmp N VADC7 ADC Data Register Low Byte Bit 7 R 0 VADC6 ADC Data Register Low Byte Bit 6 R 0 VADC5 ADC Data Register Low Byte Bit 5 R 0 VADC4 ADC Data Register Low Byte Bit 4 R 0 VADC3 ADC Data Register Low Byte Bit 3 R 0 VADC2 ADC Data Register Low Byte Bit 2 R 0 VADC1 ADC Data Register Low Byte Bit 1 R 0 VADC0 ADC Data Register Low Byte Bit 0 R 0 VADCSR The VADC Control and Status register NA 0x7A io_flag.bmp Y VADEN VADC Enable Writing this bit to one enables V-ADC Conversion. By writing it to zero, the V-ADC is turned off. Turning the V-ADC off while a conversion is in progress will terminate this conversion RW 0 VADSC VADC Satrt Conversion Write this bit to one to start a new conversion of the selected channel. VADSC will read as one as long as the conversion is not finished. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. RW 0 VADCCIF VADC Conversion Complete Interrupt Flag This bit is set when a V-ADC conversion completes and the data registers are updated.V-ADC Conversion complete Interrupt is executed if the VADCCIE bit and the I-bit in S-REG are set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on VADCSR, a pending interrupt can be disabled. RW 0 VADCCIE VADC Conversion Complete Interrupt Enable When this bit is written to one and the I-Bit in SREG is set, the V-ADC Conversion Complete Interrupt is activated RW 0 [WDTCSR] io_watch.bmp WDTCSR Watchdog Timer Control Register NA 0x60 io_flag.bmp Y WDIF Watchdog Timeout Interrupt Flag RW 0 WDIE Watchdog Timeout Interrupt Enable RW 0 WDP3 Watchdog Timer Prescaler Bit 3 RW 0 WDCE Watchdog Change Enable RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 WDOG_TIMER_PRESCALE_4BITS RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [BGCRR:BGCCR] io_analo.bmp BGCRR Bandgap Calibration of Resistor Ladder NA 0xD1 io_analo.bmp N BGCR7 Bandgap Calibration of Resistor Ladder Bit 7 RW 0 BGCR6 Bandgap Calibration of Resistor Ladder Bit 6 RW 0 BGCR5 Bandgap Calibration of Resistor Ladder Bit 5 RW 0 BGCR4 Bandgap Calibration of Resistor Ladder Bit 4 RW 0 BGCR3 Bandgap Calibration of Resistor Ladder Bit 3 RW 0 BGCR2 Bandgap Calibration of Resistor Ladder Bit 2 RW 0 BGCR1 Bandgap Calibration of Resistor Ladder Bit 1 RW 0 BGCR0 Bandgap Calibration of Resistor Ladder Bit 0 RW 0 BGCCR Bandgap Calibration Register NA 0xD0 io_analo.bmp Y BGD Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled. RW 0 BGCC5 BG Calibration of PTAT Current Bit 5 RW 0 BGCC4 BG Calibration of PTAT Current Bit 4 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 BGCC3 BG Calibration of PTAT Current Bit 3 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 BGCC2 BG Calibration of PTAT Current Bit 2 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 BGCC1 BG Calibration of PTAT Current Bit 1 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 BGCC0 BG Calibration of PTAT Current Bit 0 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 [EICRA:EIMSK:EIFR] io_ext.bmp The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level inte EICRA External Interrupt Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. NA 0x69 io_flag.bmp Y ISC21 External Interrupt Sense Control 2 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC20 External Interrupt Sense Control 2 Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW INTERRUPT_SENSE_CONTROL 0 ISC11 External Interrupt Sense Control 1 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC10 External Interrupt Sense Control 1 Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW INTERRUPT_SENSE_CONTROL 0 ISC01 External Interrupt Sense Control 0 Bit 1 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC00 External Interrupt Sense Control 0 Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW INTERRUPT_SENSE_CONTROL 0 EIMSK External Interrupt Mask Register 0x1D 0x3D io_flag.bmp Y INT2 External Interrupt Request 2 Enable When the INT2 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW 0 INT1 External Interrupt Request 1 Enable When the INT1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW 0 INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.Activity on the pin will cause an interrupt request even if INT0 is configured as an output.The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector. RW 0 EIFR External Interrupt Flag Register 0x1C 0x3C io_flag.bmp Y INTF2 External Interrupt Flag 2 When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 INTF1 External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 INTF0 External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 [PORTC:PINC] io_port.bmp AVRSimIOPort.SimIOPort PORTC Port C Data Register 0x08 0x28 io_port.bmp N PORTC0 Port C Data Register bit 0 RW 0 PINC Port C Input Pins 0x06 0x26 io_port.bmp N PINC0 Port C Input pin 0 RW 0 [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register 0x02 0x22 io_port.bmp N PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 DDRA Port A Data Direction Register 0x01 0x21 io_flag.bmp N DDA1 Data Direction Register, Port A, bit 1 RW 0 DDA0 Data Direction Register, Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. 0x00 0x20 io_port.bmp N PINA1 Input Pins, Port A bit 1 RW Hi-Z PINA0 Input Pins, Port A bit 0 RW Hi-Z [FCSR] io_analo.bmp FCSR FET Control and Status Register NA 0xF0 io_analo.bmp Y DUVRD Deep Under-Voltage Recovery Disable RW 0 CPS Current Protection Status The CPTS bit shows the status of the Current Protection. This bit is set (one) when the Current Protection Timer is activated, and is cleared (zero) when the hold-off time has elapsed. RW 0 DFE Discharge FET Enable When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Discharge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). RW 0 CFE Charge FET Enable When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Charge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). RW 0 [SPDR:SPSR:SPCR] io_com.bmp The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only) SPCR SPI Control Register 0x2c 0x4c io_flag.bmp Y SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled. RW 0 SPE SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. RW 0 DORD Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. RW 0 MSTR Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. RW 0 CPOL Clock polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information. RW 0 CPHA Clock Phase Refer to Figure 36 or Figure 37 for the functionality of this bit. RW 0 SPR1 SPI Clock Rate Select 1 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. RW 0 SPR0 SPI Clock Rate Select 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. RW COMM_SCK_RATE_3BIT 0 SPSR SPI Status Register 0x2d 0x4d io_flag.bmp Y SPIF SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR). R 0 WCOL Write Collision Flag The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. R 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading. RW 0 SPDR SPI Data Register The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. 0x2e 0x4e io_com.bmp N SPDR7 SPI Data Register bit 7 RW X SPDR6 SPI Data Register bit 6 RW X SPDR5 SPI Data Register bit 5 RW X SPDR4 SPI Data Register bit 4 RW X SPDR3 SPI Data Register bit 3 RW X SPDR2 SPI Data Register bit 2 RW X SPDR1 SPI Data Register bit 1 R 0 SPDR0 SPI Data Register bit 0 R 0 [SPMCSR] io_cpu.bmp AVRSimIOSPM.SimIOSPM The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor SPMCSR Store Program Memory Control and Status Register The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. 0x37 0x57 io_flag.bmp Y SIGRD Signature Row Read If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see “Reading the Signature Row from Software” in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used. RW 0 CTPB Clear Temporary Page Buffer When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be RW 0 RFLB Read Fuse and Lock Bits If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for detail RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec RW 0 [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Data Register, Port B 0x05 0x25 io_port.bmp N PORTB3 RW 0 PORTB2 RW 0 PORTB1 RW 0 PORTB0 RW 0 DDRB Data Direction Register, Port B 0x04 0x24 io_flag.bmp N DDB3 RW 0 DDB2 RW 0 DDB1 RW 0 DDB0 RW 0 PINB Input Pins, Port B 0x03 0x23 io_port.bmp N PINB3 R 0 PINB2 R 0 PINB1 R 0 PINB0 R 0 [SREG:SPH:SPL:MCUCR:MCUSR:FOSCCAL:OSICSR:SMCR:GPIOR2:GPIOR1:GPIOR0:DIDR0:PRR0:CLKPR] [SPH:SPL] io_cpu.bmp SREG Status Register 0x3F 0x5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R 0x3E 0x5E io_sph.bmp N SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D 0x5D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. 0x35 0x55 io_flag.bmp Y CKOE Clock Output Enable When this bit is written to one, the CPU clock divided by 4 is output on the CKOUT pin. The CKOUT pin will be tri-stated when this bit is zero. RW 0 PUD Pull-up disable When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). RW 0 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. 0x34 0x54 io_flag.bmp Y OCDRF OCD Reset Flag RW 0 WDRF Watchdog Reset Flag This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. RW 0 BODRF Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. RW 0 EXTRF External Reset Flag This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. RW 0 PORF Power-on reset flag This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. RW 0 FOSCCAL Fast Oscillator Calibration Value Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table NA 0x66 io_cpu.bmp N FCAL7 Oscillator Calibration Value Bit7 RW 0 FCAL6 Oscillator Calibration Value Bit6 RW 0 FCAL5 Oscillator Calibration Value Bit5 RW 0 FCAL4 Oscillator Calibration Value Bit4 RW 0 FCAL3 Oscillator Calibration Value Bit3 RW 0 FCAL2 Oscillator Calibration Value Bit2 RW 0 FCAL1 Oscillator Calibration Value Bit1 RW 0 FCAL0 Oscillator Calibration Value Bit0 RW 0 OSICSR Oscillator Sampling Interface Control and Status Register 0x17 0x37 io_cpu.bmp Y OSISEL0 Oscillator Sampling Interface Select 0 RW 0 OSIST Oscillator Sampling Interface Status R 0 OSIEN Oscillator Sampling Interface Enable RW 0 SMCR Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. 0x33 0x53 io_cpu.bmp Y SM2 Sleep Mode Select bit 2 These bits select between the five available sleep modes. RW 0 SM1 Sleep Mode Select bit 1 These bits select between the five available sleep modes. RW 0 SM0 Sleep Mode Select bit 0 These bits select between the five available sleep modes. RW 0 SE Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To RW 0 GPIOR2 General Purpose IO Register 2 The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2B 0x4B io_cpu.bmp N GPIOR27 General Purpose IO Register 2 bit 7 RW 0 GPIOR26 General Purpose IO Register 2 bit 6 RW 0 GPIOR25 General Purpose IO Register 2 bit 5 RW 0 GPIOR24 General Purpose IO Register 2 bit 4 RW 0 GPIOR23 General Purpose IO Register 2 bit 3 RW 0 GPIOR22 General Purpose IO Register 2 bit 2 RW 0 GPIOR21 General Purpose IO Register 2 bit 1 RW 0 GPIOR20 General Purpose IO Register 2 bit 0 RW 0 GPIOR1 General Purpose IO Register 1 The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2A 0x4A io_cpu.bmp N GPIOR17 General Purpose IO Register 1 bit 7 RW 0 GPIOR16 General Purpose IO Register 1 bit 6 RW 0 GPIOR15 General Purpose IO Register 1 bit 5 RW 0 GPIOR14 General Purpose IO Register 1 bit 4 RW 0 GPIOR13 General Purpose IO Register 1 bit 3 RW 0 GPIOR12 General Purpose IO Register 1 bit 2 RW 0 GPIOR11 General Purpose IO Register 1 bit 1 RW 0 GPIOR10 General Purpose IO Register 1 bit 0 RW 0 GPIOR0 General Purpose IO Register 0 The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x1E 0x3E io_cpu.bmp N GPIOR07 General Purpose IO Register 0 bit 7 RW 0 GPIOR06 General Purpose IO Register 0 bit 6 RW 0 GPIOR05 General Purpose IO Register 0 bit 5 RW 0 GPIOR04 General Purpose IO Register 0 bit 4 RW 0 GPIOR03 General Purpose IO Register 0 bit 3 RW 0 GPIOR02 General Purpose IO Register 0 bit 2 RW 0 GPIOR01 General Purpose IO Register 0 bit 1 RW 0 GPIOR00 General Purpose IO Register 0 bit 0 RW 0 DIDR0 Digital Input Disable Register NA 0x7E io_cpu.bmp Y PA1DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. RW 0 PA0DID When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. RW 0 PRR0 Power Reduction Register 0 NA 0x64 io_cpu.bmp Y PRVRM Power Reduction Voltage Regulator Monitor RW 0 PRSPI Power reduction SPI RW 0 PRTIM1 Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the, Timer/Counter1 is enabled, operation will continue like before the shutdown. RW 0 PRTIM0 Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. RW 0 PRVADC Power Reduction V-ADC Writing a logic one to this bit shuts down the V-ADC. The V-ADC must be disabled before shut down. RW 0 CLKPR Clock Prescale Register NA 0x61 io_cpu.bmp Y CLKPCE Clock Prescaler Change Enable RW 0 CLKPS1 Clock Prescaler Select Bit 1 RW 1 CLKPS0 Clock Prescaler Select Bit 0 RW 1 [BPPLR:BPCR:BPHCTR:BPOCTR:BPSCTR:BPCHCD:BPDHCD:BPCOCD:BPDOCD:BPSCD:BPIFR:BPIMSK] io_analo.bmp BPPLR Battery Protection Parameter Lock Register NA 0xFE io_analo.bmp Y BPPLE Battery Protection Parameter Lock Enable RW 0 BPPL Battery Protection Parameter Lock RW 0 BPCR Battery Protection Control Register NA 0xFD io_analo.bmp Y SCD Short Circuit Protection Disabled RW 0 DOCD Discharge Over-current Protection Disabled RW 0 COCD Charge Over-current Protection Disabled RW 0 DHCD Discharge High-current Protection Disable RW 0 CHCD Charge High-current Protection Disable RW 0 BPHCTR Battery Protection Short-current Timing Register NA 0xFC io_analo.bmp N HCPT5 High-current Protection Timing bit 5 RW 0 HCPT4 High-current Protection Timing bit 4 RW 0 HCPT3 High-current Protection Timing bit 3 RW 0 HCPT2 High-current Protection Timing bit 2 RW 0 HCPT1 High-current Protection Timing bit 1 RW 0 HCPT0 High-current Protection Timing bit 0 RW 0 BPOCTR Battery Protection Over-current Timing Register NA 0xFB io_analo.bmp N OCPT5 Over-current Protection Timing bit 5 These bits control the delay of the Over-circuit Protection. RW 0 OCPT4 Over-current Protection Timing bit 4 These bits control the delay of the Over-circuit Protection. RW 0 OCPT3 Over-current Protection Timing bit 3 These bits control the delay of the Over-circuit Protection. RW 0 OCPT2 Over-current Protection Timing bit 2 These bits control the delay of the Over-circuit Protection. RW 0 OCPT1 Over-current Protection Timing bit 1 These bits control the delay of the Over-circuit Protection. RW 1 OCPT0 Over-current Protection Timing bit 0 These bits control the delay of the Over-circuit Protection. RW 0 BPSCTR Battery Protection Short-current Timing Register NA 0xFA io_analo.bmp N SCPT6 Short-current Protection Timing RW 0 SCPT5 Short-current Protection Timing RW 0 SCPT4 Short-current Protection Timing RW 1 SCPT3 Short-current Protection Timing RW 0 SCPT2 Short-current Protection Timing RW 0 SCPT1 Short-current Protection Timing RW 0 SCPT0 Short-current Protection Timing RW 0 BPCHCD Battery Protection Charge-High-current Detection Level Register NA 0xF9 io_analo.bmp N CHCDL7 Charge High-current Detection Level These bits sets the RSENSE voltage level for detection of Charge High-current RW 1 CHCDL6 Charge High-current Detection Level These bits sets the RSENSE voltage level for detection of Charge High-current RW 1 CHCDL5 Charge High-current Detection Level These bits sets the RSENSE voltage level for detection of Charge High-current RW 0 CHCDL4 Charge High-current Detection Level These bits sets the RSENSE voltage level for detection of Charge High-current RW 0 CHCDL3 Charge High-current Detection Level These bits sets the RSENSE voltage level for detection of Charge High-current RW 1 CHCDL2 Charge High-current Detection Level These bits sets the RSENSE voltage level for detection of Charge High-current RW 1 CHCDL1 Charge High-current Detection Level These bits sets the RSENSE voltage level for detection of Charge High-current RW 1 CHCDL0 Charge High-current Detection Level These bits sets the RSENSE voltage level for detection of Charge High-current RW 1 BPDHCD Battery Protection Discharge-High-current Detection Level Register NA 0xF8 io_analo.bmp N DHCDL7 Discharge High-current Detection Level bit 7 RW 1 DHCDL6 Discharge High-current Detection Level bit 6 RW 1 DHCDL5 Discharge High-current Detection Level bit 5 RW 1 DHCDL4 Discharge High-current Detection Level bit 4 RW 1 DHCDL3 Discharge High-current Detection Level bit 3 RW 0 DHCDL2 Discharge High-current Detection Level bit 2 RW 0 DHCDL1 Discharge High-current Detection Level bit 1 RW 1 DHCDL0 Discharge High-current Detection Level bit 0 1 RW BPCOCD Battery Protection Charge-Over-current Detection Level Register NA 0xF7 io_analo.bmp N COCDL7 Charge Over-current Detection Level RW 1 COCDL6 Charge Over-current Detection Level RW 1 COCDL5 Charge Over-current Detection Level RW 1 COCDL4 Charge Over-current Detection Level RW 1 COCDL3 Charge Over-current Detection Level RW 0 COCDL2 Charge Over-current Detection Level RW 0 COCDL1 Charge Over-current Detection Level RW 1 COCDL0 Charge Over-current Detection Level RW 1 BPDOCD Battery Protection Discharge-Over-current Detection Level Register NA 0xF6 io_analo.bmp N DOCDL7 Discharge Over-current Detection Level bit7 RW 1 DOCDL6 Discharge Over-current Detection Level bit6 RW 1 DOCDL5 Discharge Over-current Detection Level bit5 RW 1 DOCDL4 Discharge Over-current Detection Level bit4 RW 1 DOCDL3 Discharge Over-current Detection Level bit3 RW 0 DOCDL2 Discharge Over-current Detection Level bit2 RW 0 DOCDL1 Discharge Over-current Detection Level bit1 RW 1 DOCDL0 Discharge Over-current Detection Level bit0 RW 1 BPSCD Battery Protection Short-Circuit Detection Level Register NA 0xF5 io_analo.bmp N SCDL7 Short-circuit Detection Level bit 7 RW 1 SCDL6 Short-circuit Detection Level bit 6 RW 1 SCDL5 Short-circuit Detection Level bit 5 RW 1 SCDL4 Short-circuit Detection Level bit 4 RW 1 SCDL3 Short-circuit Detection Level bit 3 RW 0 SCDL2 Short-circuit Detection Level bit 2 RW 0 SCDL1 Short-circuit Detection Level bit 1 RW 1 SCDL0 Short-circuit Detection Level bit 0 RW 1 BPIFR Battery Protection Interrupt Flag Register NA 0xF3 io_analo.bmp Y SCIF Short-circuit Protection Activated Interrupt Flag RW 0 DOCIF Discharge Over-current Protection Activated Interrupt Flag RW 0 COCIF Charge Over-current Protection Activated Interrupt Flag RW 0 DHCIF Disharge High-current Protection Activated Interrupt RW 0 CHCIF Charge High-current Protection Activated Interrupt RW 0 BPIMSK Battery Protection Interrupt Mask Register NA 0xF2 io_analo.bmp Y SCIE Short-circuit Protection Activated Interrupt Enable RW 0 DOCIE Discharge Over-current Protection Activated Interrupt Enable RW 0 COCIE Charge Over-current Protection Activated Interrupt Enable RW 0 DHCIE Discharger High-current Protection Activated Interrupt RW 0 CHCIE Charger High-current Protection Activated Interrupt RW 0 [EEAR:EEDR:EECR] io_cpu.bmp EEPROM_02.xml EEAR EEARL EEPROM Read/Write Access The EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction 0x21 0x41 io_cpu.bmp N EEAR7 EEPROM Read/Write Access bit 7 RW 0 EEAR6 EEPROM Read/Write Access bit 6 RW 0 EEAR5 EEPROM Read/Write Access bit 5 RW 0 EEAR4 EEPROM Read/Write Access bit 4 RW 0 EEAR3 EEPROM Read/Write Access bit 3 RW 0 EEAR2 EEPROM Read/Write Access bit 2 RW 0 EEAR1 EEPROM Read/Write Access bit 1 RW 0 EEAR0 EEPROM Read/Write Access bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 0x20 0x40 io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register 0x1F 0x3F io_flag.bmp Y EEPM1 RW 0 EEPM0 RW EEP_MODE 0 EERIE EEProm Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero). RW 0 EEMPE EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. RW 0 EEPE EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. RW 0 EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined. RW 0 [TCCR1A:TCCR1B:TCNT1H:TCNT1L:OCR1A:OCR1B:TIMSK1:TIFR1:GTCCR] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL] io_timer.bmp TCCR1B Timer/Counter1 Control Register B NA 0x81 io_flag.bmp Y CS12 Clock Select1 bit 2 RW 0 CS11 Clock Select1 bit 1 RW 0 CS10 Clock Select1 bit 0 RW 0 TCCR1A Timer/Counter 1 Control Register A NA 0x80 io_flag.bmp Y TCW1 Timer/Counter Width When this bit is written to one 16-bit mode is selected. RW 0 ICEN1 Input Capture Mode Enable The Input Capture Mode is enabled when this bit is written to one. RW 0 ICNC1 Input Capture Noise Canceler Setting this bit activates the Input Capture Noise Canceler. RW 0 ICES1 Input Capture Edge Select This bit selects which edge on the Input Capture Source that is used to trigger a capture event. RW 0 ICS1 Input Capture Select When written logic one, this bit enables the input capture function in Timer/Counter to be triggered by the alternative Input Capture Source. RW 0 WGM10 Waveform Generation Mode This bit controls the counting sequence of the counter RW 0 TCNT1H Timer Counter 1 High Byte NA 0x85 io_timer.bmp N TCNT1H7 Timer Counter 1 High Byte bit 7 RW 0 TCNT1H6 Timer Counter 1 High Byte bit 6 RW 0 TCNT1H5 Timer Counter 1 High Byte bit 5 RW 0 TCNT1H4 Timer Counter 1 High Byte bit 4 RW 0 TCNT1H3 Timer Counter 1 High Byte bit 3 RW 0 TCNT1H2 Timer Counter 1 High Byte bit 2 RW 0 TCNT1H1 Timer Counter 1 High Byte bit 1 RW 0 TCNT1H0 Timer Counter 1 High Byte bit 0 RW 0 TCNT1L Timer Counter 1 Low Byte NA 0x84 io_timer.bmp N TCNT1L7 Timer Counter 1 Low Byte bit 7 RW 0 TCNT1L6 Timer Counter 1 Low Byte bit 6 RW 0 TCNT1L5 Timer Counter 1 Low Byte bit 5 RW 0 TCNT1L4 Timer Counter 1 Low Byte bit 4 RW 0 TCNT1L3 Timer Counter 1 Low Byte bit 3 RW 0 TCNT1L2 Timer Counter 1 Low Byte bit 2 RW 0 TCNT1L1 Timer Counter 1 Low Byte bit 1 RW 0 TCNT1L0 Timer Counter 1 Low Byte bit 0 RW 0 OCR1A Output Compare Register 1A The Output Compare Register A contains an 8-bit value that is continuously compared with the NA 0x88 io_timer.bmp N OCR1A7 RW 0 OCR1A6 RW 0 OCR1A5 RW 0 OCR1A4 RW 0 OCR1A3 RW 0 OCR1A2 RW 0 OCR1A1 RW 0 OCR1A0 RW 0 OCR1B Output Compare Register B NA 0x89 io_timer.bmp N OCR1B7 RW 0 OCR1B6 RW 0 OCR1B5 RW 0 OCR1B4 RW 0 OCR1B3 RW 0 OCR1B2 RW 0 OCR1B1 RW 0 OCR1B0 RW 0 TIMSK1 Timer/Counter Interrupt Mask Register NA 0x6F io_flag.bmp Y ICIE1 Timer/Counter n Input Capture Interrupt Enable RW 0 OCIE1B Timer/Counter1 Output Compare B Interrupt Enable RW 0 OCIE1A Timer/Counter1 Output Compare A Interrupt Enable RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable RW 0 TIFR1 Timer/Counter Interrupt Flag register 0x16 0x36 io_flag.bmp Y ICF1 Timer/Counter 1 Input Capture Flag RW 0 OCF1B Timer/Counter1 Output Compare Flag B RW 0 OCF1A Timer/Counter1 Output Compare Flag A RW 0 TOV1 Timer/Counter1 Overflow Flag RW 0 GTCCR General Timer/Counter Control Register 0x23 0x43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode RW 0 PSRSYNC Prescaler Reset RW 0 [CADCSRA:CADCSRB:CADICH:CADICL:CADAC3:CADAC2:CADAC1:CADAC0:CADRC] [CADICH:CADICL];[CADAC3:CADAC2:CADAC1:CADAC0] io_analo.bmp CoulombCounter_m406 CADCSRA CC-ADC Control and Status Register A NA 0xE4 io_analo.bmp Y CADEN When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW 0 CADPOL RW 0 CADUB CC_ADC Update Busy RW 0 CADAS1 CC_ADC Accumulate Current Select Bit 1 The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual. RW 0 CADAS0 CC_ADC Accumulate Current Select Bit 0 The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual. RW 0 CADSI1 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADSI0 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADSE When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. RW 0 CADCSRB CC-ADC Control and Status Register B NA 0xE5 io_analo.bmp Y CADACIE CC-ADC Accumulate Current Interrupt Enable RW 0 CADRCIE Regular Current Interrupt Enable When the CADACIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Accumulate Current Interrupt is enabled. RW 0 CADICIE CAD Instantenous Current Interrupt Enable The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADACIF CC-ADC Accumulate Current Interrupt Flag The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag. RW 0 CADRCIF CC-ADC Accumulate Current Interrupt Flag The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag. RW 0 CADICIF CC-ADC Instantaneous Current Interrupt Flag The CADICIF bit is set (one) when a CC-ADC Instantaneous Current conversion is completed. The CC-ADC Instantaneous Current Interrupt is executed if the CADICIE bit and the I-bit in SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag. RW 0 CADICH CC-ADC Instantaneous Current NA 0xE9 io_analo.bmp N CADICH7 When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW 0 CADICH6 RW 0 CADICH5 RW 0 CADICH4 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADICH3 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADICH2 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADICH1 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADICH0 When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. RW 0 CADICL CC-ADC Instantaneous Current NA 0xE8 io_analo.bmp N CADICL7 When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW 0 CADICL6 RW 0 CADICL5 RW 0 CADICL4 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADICL3 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADICL2 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADICL1 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADICL0 When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. RW 0 CADAC3 ADC Accumulate Current NA 0xE3 io_analo.bmp N CADAC31 R 0 CADAC30 R 0 CADAC29 R 0 CADAC28 R 0 CADAC27 R 0 CADAC26 R 0 CADAC25 R 0 CADAC24 R 0 CADAC2 ADC Accumulate Current NA 0xE2 io_analo.bmp N CADAC23 R 0 CADAC22 R 0 CADAC21 R 0 CADAC20 R 0 CADAC19 R 0 CADAC18 R 0 CADAC17 R 0 CADAC16 R 0 CADAC1 ADC Accumulate Current NA 0xE1 io_analo.bmp N CADAC15 R 0 CADAC14 R 0 CADAC13 R 0 CADAC12 R 0 CADAC11 R 0 CADAC10 R 0 CADAC09 R 0 CADAC08 R 0 CADAC0 ADC Accumulate Current NA 0xE0 io_analo.bmp N CADAC07 R 0 CADAC06 R 0 CADAC05 R 0 CADAC04 R 0 CADAC03 R 0 CADAC02 R 0 CADAC01 R 0 CADAC00 R 0 CADRC CC-ADC Regular Current he CC-ADC Regular Current Register determines the threshold level for the Regular Current NA 0xE6 io_analo.bmp N CADRC7 RW 0 CADRC6 RW 0 CADRC5 RW 0 CADRC4 RW 0 CADRC3 RW 0 CADRC2 RW 0 CADRC1 RW 0 CADRC0 RW 0 [TCCR0A:TCCR0B:TCNT0H:TCNT0L:OCR0A:OCR0B:TIMSK0:TIFR0] [TCNT0H:TCNT0L] io_timer.bmp timer8_megaD TCCR0A Timer/Counter0 Control Register 0x24 0x44 io_flag.bmp Y TCW0 Timer/Counter Width RW 0 ICEN0 Input Capture Mode Enable RW 0 ICNC0 Input Capture Noise Canceler RW 0 ICES0 Input Capture Edge Select RW 0 ICS0 Input Capture Select RW 0 WGM00 Clock Select0 bit 0 RW 0 TCCR0B Timer/Counter0 Control Register 0x25 0x45 io_flag.bmp Y CS02 Clock Select0 bit 2 RW 0 CS01 Clock Select0 bit 1 RW 0 CS00 Clock Select0 bit 0 RW 0 TCNT0H Timer Counter 0 High Byte The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. 0x27 0x47 io_timer.bmp N TCNT0H7 Timer Counter 0 bit 7 RW 0 TCNT0H6 Timer Counter 0 bit 6 RW 0 TCNT0H5 Timer Counter 0 bit 5 RW 0 TCNT0H4 Timer Counter 0 bit 4 RW 0 TCNT0H3 Timer Counter 0 bit 3 RW 0 TCNT0H2 Timer Counter 0 bit 2 RW 0 TCNT0H1 Timer Counter 0 bit 1 RW 0 TCNT0H0 Timer Counter 0 bit 0 RW 0 TCNT0L Timer Counter 0 Low Byte 0x26 0x46 io_timer.bmp N TCNT0L7 Timer Counter 0 bit 6 Low byte RW 0 TCNT0L6 Timer Counter 0 bit 6 Low byte RW 0 TCNT0L5 Timer Counter 0 bit 5 Low byte RW 0 TCNT0L4 Timer Counter 0 bit 4 Low byte RW 0 TCNT0L3 Timer Counter 0 bit 3 Low byte RW 0 TCNT0L2 Timer Counter 0 bit 2 Low byte RW 0 TCNT0L1 Timer Counter 0 bit 1 Low byte RW 0 TCNT0L0 Timer Counter 0 bit 0 Low byte RW 0 OCR0A Output compare Register A 0x28 0x48 io_timer.bmp N OCR0A7 RW 0 OCR0A6 RW 0 OCR0A5 RW 0 OCR0A4 RW 0 OCR0A3 RW 0 OCR0A2 RW 0 OCR0A1 RW 0 OCR0A0 RW 0 OCR0B Output compare Register B 0x29 0x49 io_timer.bmp N OCR0B7 RW 0 OCR0B6 RW 0 OCR0B5 RW 0 OCR0B4 RW 0 OCR0B3 RW 0 OCR0B2 RW 0 OCR0B1 RW 0 OCR0B0 RW 0 TIMSK0 Timer/Counter Interrupt Mask Register NA 0x6E io_flag.bmp Y ICIE0 Timer/Counter n Input Capture Interrupt Enable RW 0 OCIE0B Output Compare Interrupt Enable RW 0 OCIE0A Output Compare Interrupt Enable RW 0 TOIE0 Overflow Interrupt Enable RW 0 TIFR0 Timer/Counter Interrupt Flag register 0x15 0x35 io_flag.bmp Y ICF0 Timer/Counter Interrupt Flag Register RW 0 OCF0B Output Compare Flag RW 0 OCF0A Output Compare Flag RW 0 TOV0 Overflow Flag RW 0 [ROCR] io_analo.bmp ROCR Regulator Operating Condition Register NA 0xC8 io_analo.bmp Y ROCS ROC Status R 0 ROCWIF ROC Warning Interrupt Flag RW 0 ROCWIE ROC Warning Interrupt Enable RW 0 [JTAGICEmkII:STK500_2:AVRDragon:AVRISPmkII:SIMULATOR:AVRONE:SIMULATOR2] 0x9310 DebugWire 0x7F,0x01,0xE0,0xF0,0xFB,0x3F,0xB8,0xE0 0x37,0x01,0x00,0xE0,0xFB,0x1F,0xA8,0xE0 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x53,0xC2,0x00,0x57,0x33,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x03,0x00,0x7F,0x03,0xED,0x7F 0x50,0xC2,0x00,0x50,0x33,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x70,0x00,0xED,0x3F 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00 0x57 0x00 0x80 0x04 0 0 0 0 0 0xFE 0x4000 0x00,32 0x20,64 0x00 0x00 0x10 0x00 0x00 0x20 0xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF 0xB6,0x01,0x11 0x3E 0x3D 0x31 0x00 0x00 0x00 0x00 0x00 0x3F 200 100 25 32 0 3 0x53 1 1 20 1 0x41 128 10 0x40 0x4C 0x00 0x00 0x00 0x41 4 20 0xC1 0xC2 0x00 0x00 0x00 256 256 4 4 4 4 0x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x66 0x68 0x78 0x68 0x68 0x7A 0x6A 0x68 0x78 0x78 0x7D 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x0F 100 0 6 1 1 25 1 70 101 26 40 1 0x0D 256 6 256 0x05 256 5 256 25 25 AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 13 0x28 0 AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort N AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0006 0x1D 0x01 0x1c 0x01 0x00 0x01 0x69 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0008 0x1D 0x02 0x1C 0x02 0x03 0x04 0x69 0x0c AVRSimIOExtInterrupt.SimIOExtInterrupt 0x000a 0x1D 0x04 0x1C 0x04 0x03 0x08 0x69 0x30 AVRSimIOSPM.SimIOSPM N/A 0xFD 0xff 0xDF 0xff AvrMasterTimer.MasterTimer 0x1c 0x18 0x1a 0x16 0x08 0x01 1:8:64:256:1024 AvrMasterTimer.MasterTimer 0x14 0x10 0x12 0x0e 0xf3 0x1f 1:8:64:256:1024 AVRSimIOSpi.SimIOSpi 0x1e 0x03 0x02 0x03 0x08 0x03 0x04 0x03 0x04 0x01 AVRSimADC.SimADC 0x20 0x9310 DebugWire libATmega16HVA2.dll