[CORE:PROGVOLT:POWER:LOCKBIT:MEMORY:INTERRUPT_VECTOR:PACKAGE:ADMIN:PROGRAMMING:FUSE:IO_MODULE:ICE_SETTINGS]V2EAVRSimCoreV2.SimCoreV2[][][]32$00$1B$1A$1D$1C$1F$1E2.76.04.55.54MHz25CTBD mATBD mATBD uA[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled6110x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabled0x0C0x0CApplication Protection Mode 1: No lock on SPM and LPM in Application Section0x0C0x08Application Protection Mode 2: SPM prohibited in Application Section0x0C0x00Application Protection Mode 3: LPM and SPM prohibited in Application Section0x0C0x04Application Protection Mode 4: LPM prohibited in Application Section0x300x30Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section0x300x20Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section0x300x00Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section0x300x10Boot Loader Protection Mode 4: LPM prohibited in Boot Loader SectionLB1Lock bitLB2Lock bitBLB01Boot Lock bitBLB02Boot Lock bitBLB11Boot lock bitBLB12Boot lock bitAVRSimMemory8bit.SimMemory8bit6553620484096$01000$0$0000$003F$0060$00FF$0020$00FFNA$FA0x010x020x040x080x100x200x400x80NA$F90x010x020x040x080x100x200x400x80NA$F80x010x020x040x080x100x200x400x80NA$F70x010x020x040x080x100x200x400x80NA$F60x010x020x040x080x100x200x400x80NA$F50x010x020x040x080x100x200x400x80NA$F40x010x040x080x100x200x400x80NA$F30x010x020x040x080x100x200x400x80NA$F20x010x020x040x080x100x200x400x80NA$F10x010x020x040x080x100x200x400x80NA$F00x010x020x040x080x100x200x400x80NA$EF0x010x020x040x080x100x200x400x80NA$EE0x010x020x040x080x100x200x400x80NA$ED0x010x020x040x080x100x200x400x80NA0xEC0x010x020x040x080x100x200x400x80NA0xEB0x010x020x040x080x100x200x400x80NA0xEA0x010x020x040x080x100x200x400x80NA0xE90x010x020x040x080x100x200x400x80NA0xE80x010x020x040x080x100x200x400x80NA0xE70x010x020x040x080x100x200x400x80NA0xE60x010x020x040x080x100x200x400x80NA0xE50x010x020x040x080x100x200x400x80NA0xE40x010x020x040x080x100x200x40NA0xE30x020x040x080x200x40NA0xE20x020x040x080x100x200x40NA0xE1NA0xE00x010x020x040x080x100x20NA0xDFNA0xDE0x010x020x040x080x100x20NA0xDDNA0xDC0x010x020x040x080x100x20NA0xDB0x010x020x040x080x100x200x400x80NA0xDA0x010x020x040x080x100x200x400x80NA0xD90x010x020x040x080x100x40NA0xD80x010x020x040x080x100x200x400x80NA0xD20x010x020x040x080x100x200x400x80NA0xD10x010x020x040x08NA0xD00x010x020x040x080x100x200x400x80NA0xCF0x010x020x040x080x100x200x400x80NA0xCE0x010x020x040x08NA0xCD0x010x020x040x080x100x200x400x80NA0xCC0x010x020x040x080x100x200x80NA0xCB0x010x020x040x080x100x200x400x80NA0xCA0x010x020x040x08NA0xC90x010x020x040x080x100x200x400x80NA0xC80x010x020x040x080x100x200x400x80NA$BC0x010x020x040x08NA$BB0x010x020x040x08NA$BA0x010x020x040x080x100x200x400x80NA$B90x010x020x040x080x100x200x400x80NA$B80x010x020x040x080x100x200x400x80NA$B70x010x020x200x400x80NA$B60x010x020x040x080x100x20NA$B50x040x080x100x20NA$B40x010x020x040x080x100x20NA$B30x010x020x040x08NA$B20x010x020x040x080x100x200x400x80NA$B10x010x020x040x08NA$B00x010x020x040x080x100x200x400x80NA$AF0x010x020x040x08NA$AE0x010x020x040x080x100x200x400x80NA$AD0x010x020x040x08NA$AC0x010x020x040x080x100x200x400x80NA$AB0x010x020x040x08NA$AA0x010x020x040x080x100x200x400x80NA$A90x010x020x040x08NA$A80x010x020x040x080x100x200x400x80NA$A70x010x020x040x08NA$A60x010x020x040x080x100x200x400x80NA$A50x010x020x040x08NA$A40x010x020x040x080x100x200x400x80NA$A30x010x020x040x08NA$A20x010x020x040x080x100x200x400x80NA$A10x010x020x040x08NA$A00x010x020x040x080x100x200x400x80NA$970x010x020x040x100x200x400x80NA$960x010x020x040x100x200x400x80NA$950x010x020x040x080x100x200x400x80NA$940x010x020x040x080x100x200x400x80NA$920x010x020x040x080x100x200x400x80NA$910x010x020x040x080x100x200x400x80NA$900x010x040x100x200x400x80NA$8B0x010x020x040x080x100x200x400x80NA$8A0x010x020x040x080x100x200x400x80NA$890x010x020x040x080x100x200x400x80NA$880x010x020x040x080x100x200x400x80NA$870x010x020x040x080x100x200x400x80NA$860x010x020x040x080x100x200x400x80NA$850x010x020x040x080x100x200x400x80NA$840x010x020x040x080x100x200x400x80NA$820x400x80NA$810x010x020x040x080x100x400x80NA$800x010x020x100x200x400x80NA$7F0x010x020x040x080x100x200x40NA$7E0x010x020x040x080x100x200x400x80NA$7C0x010x020x040x080x100x200x400x80NA$7B0x010x020x040x080x200x400x80NA$7A0x010x020x040x080x100x200x400x80NA$790x010x020x040x080x100x200x400x80NA$780x010x020x040x080x100x200x400x80NA$770x010x020x040x080x100x200x400x80NA$760x010x020x040x080x100x200x400x80NA$750x010x020x040x080x100x200x400x80NA$6F0x010x020x040x20NA$6E0x010x020x04NA$6D0x010x020x04NA$6C0x010x020x040x080x100x200x400x80NA$6B0x010x020x040x080x100x200x400x80NA$6A0x010x020x040x080x100x200x400x80NA$690x010x020x040x080x100x200x400x80NA$680x010x020x040x08NA$660x010x020x040x080x100x200x40NA$640x010x020x040x080x100x200x40NA$610x010x020x040x080x80NA$600x010x020x040x080x100x200x400x80$3F$5F0x010x020x040x080x100x200x400x80$3E$5E0x010x020x040x080x100x200x400x80$3D$5D0x010x020x040x080x100x200x400x80$37$570x010x020x040x080x100x200x400x80$35$550x010x020x100x80$34$540x010x020x040x08$33$530x010x020x040x08$31$51$30$500x010x020x040x080x100x200x400x80$2E$4E0x010x020x040x080x100x200x400x80$2D$4D0x010x400x80$2C$4C0x010x020x040x080x100x200x400x80$29$490x010x020x04$28$480x010x020x040x080x100x200x400x80$27$470x010x020x040x080x100x200x400x80$26$460x010x020x040x080x100x200x400x80$25$450x010x020x040x080x400x80$24$440x010x020x100x200x400x80$23$430x010x400x800x01$22$420x010x020x04$21$410x010x020x040x080x100x200x400x80$20$400x010x020x040x080x100x200x400x80$1F$3F0x010x020x040x080x100x20$1E$3E0x010x020x040x080x100x200x400x80$1D$3D0x010x020x040x08$1C$3C0x010x020x040x08$1B$3B0x010x020x040x08$1A$3A0x010x020x040x080x100x200x400x80$19$390x010x020x040x080x100x200x400x80$16$360x010x020x040x20$15$350x010x020x04$0E$2E0x010x020x04$0D$2D0x010x020x04$0C$2C0x010x020x04$0B$2B0x010x020x040x080x100x200x400x80$0A$2A0x010x020x040x080x100x200x400x80$09$290x010x020x040x080x100x200x400x80$08$280x010x020x040x080x100x200x400x80$07$270x010x020x040x080x100x200x400x80$06$260x010x020x040x080x100x200x400x80$05$250x010x020x040x080x100x200x400x80$04$240x010x020x040x080x100x200x400x80$03$230x010x020x040x080x100x200x400x80$7000$7FFF$0$6FFF1285124$0$7E00$7E0010248$0$7C00$7C00204816$0$7800$7800409632$0$7000$700031AVRSimInterrupt.SimInterrupt$0000RESETExternal Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset$0002ANACOMP0Analog Comparator 0$0004ANACOMP1Analog Comparator 1$0006ANACOMP2Analog Comparator 2$0008ANACOMP3Analog Comparator 3$000APSC FAULTPSC Fault$000CPSC ECPSC End of Cycle$000EINT0External Interrupt Request 0$0010INT1External Interrupt Request 1$0012INT2External Interrupt Request 2$0014INT3External Interrupt Request 3$0016TIMER1 CAPTTimer/Counter1 Capture Event$0018TIMER1 COMPATimer/Counter1 Compare Match A$001ATIMER1 COMPBTimer/Counter1 Compare Match B$001CTIMER1 OVFTimer1/Counter1 Overflow$001ETIMER0 COMPATimer/Counter0 Compare Match A$0020TIMER0 COMPBTimer/Counter0 Compare Match B$0022TIMER0 OVFTimer/Counter0 Overflow$0024CAN INTCAN MOB, Burst, General Errors$0026CAN TOVFCAN Timer Overflow$0028LIN TCLIN Transfer Complete$002ALIN ERRLIN Error$002CPCINT0Pin Change Interrupt Request 0$002EPCINT1Pin Change Interrupt Request 1$0030PCINT2Pin Change Interrupt Request 2$0032PCINT3Pin Change Interrupt Request 3$0034SPI, STCSPI Serial Transfer Complete$0036ADCADC Conversion Complete$0038WDTWatchdog Time-Out Interrupt$003AEE READYEEPROM Ready$003CSPM READYStore Program Memory Read[QFN:SOIC]32[PD2:PSCIN2:OC1A:MISO_A:PCINT18][PD3:TXD:TXLIN:OC0A:SS:MOSI_A:PCINT19][PC1:PSCIN1:OC1B:SS_A:PCINT9][VCC][GND][PC2:T0:TXCAN:PCINT10][PC3:T1:RXCAN:ICP1B:PCINT11][PB0:MISO:PSCOUT2A:PCINT0][PB1:MOSI:PSCOUT2B:PCINT1][PE1:OC0B:XTAL1:PCINT25][PE2:ADC0:XTAL2:PCINT26][PD4:ADC1:RXD:RXLIN:ICP1A:SCK_A:PCINT20][PD5:ADC2:ACMP2:PCINT21][PD6:ADC3:ACMPN2:INT0:PCINT22][PD7:ACMP0:PCINT23][PB2:ADC5:INT1:ACMPN0:PCINT2][PC4:ADC8:AMP1-:ACMPN3:PCINT12][PC5:ADC9:AMP1+:ACMP3:PCINT13][AVCC][AGND][AREF][PC6:ADC10:ACMP1:PCINT14][PB3:AMP0-:PCINT3][PB4:AMP0+:PCINT4][PC7:D2A:AMP2+:PCINT15][PB5:ADC6:INT2:ACMPN1:AMP2-:PCINT5][PB6:ADC7:PSCOUT1B:PCINT6][PB7:ADC4:PSCOUT0B:SCK:PCINT7][PD0:PSCOUT0A:PCINT16][PC0:INT3:PSCOUT1A:PCINT8][PE0:RESET:OCD:PCINT24][PD1:PSCIN0:CLK0:PCINT17]32[PD2:PSCIN2:OC1A:MISO_A:PCINT18][PD3:TXD:TXLIN:OC0A:SS:MOSI_A:PCINT19][PC1:PSCIN1:OC1B:SS_A:PCINT9][VCC][GND][PC2:T0:TXCAN:PCINT10][PC3:T1:RXCAN:ICP1B:PCINT11][PB0:MISO:PSCOUT2A:PCINT0][PB1:MOSI:PSCOUT2B:PCINT1][PE1:OC0B:XTAL1:PCINT25][PE2:ADC0:XTAL2:PCINT26][PD4:ADC1:RXD:RXLIN:ICP1A:SCK_A:PCINT20][PD5:ADC2:ACMP2:PCINT21][PD6:ADC3:ACMPN2:INT0:PCINT22][PD7:ACMP0:PCINT23][PB2:ADC5:INT1:ACMPN0:PCINT2][PC4:ADC8:AMP1-:ACMPN3:PCINT12][PC5:ADC9:AMP1+:ACMP3:PCINT13][AVCC][AGND][AREF][PC6:ADC10:ACMP1:PCINT14][PB3:AMP0-:PCINT3][PB4:AMP0+:PCINT4][PC7:D2A:AMP2+:PCINT15][PB5:ADC6:INT2:ACMPN1:AMP2-:PCINT5][PB6:ADC7:PSCOUT1B:PCINT6][PB7:ADC4:PSCOUT0B:SCK:PCINT7][PD0:PSCOUT0A:PCINT16][PC0:INT3:PSCOUT1A:PCINT8][PE0:RESET:OCD:PCINT24][PD1:PSCIN0:CLK0:PCINT17]ATmega64M18MHz1RELEASED$1E$96$8410x31000x000xff,0xdf,0xff0xff,0xdf,0xff1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!0x00,8.0 MHz2568[LOW:HIGH:EXTENDED]8CKDIV8Divide clock by 80CKOUTOscillator output option1SUT1Select start-up time0SUT0Select start-up time0CKSEL3Select Clock Source0CKSEL2Select Clock Source0CKSEL1Select Clock Source0CKSEL0Select Clock Source1550x800x00Divide clock by 8 internally; [CKDIV8=0]0x400x00Clock output on PORTD1; [CKOUT=0]0x3F0x00Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00]0x3F0x10Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01]0x3F0x20Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10]0x3F0x02Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00]0x3F0x12Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0010 SUT=01]0x3F0x22Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0010 SUT=10]; default value0x3F0x08Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F0x18Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F0x28Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F0x38Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F0x09Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F0x19Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F0x29Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F0x39Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F0x0AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F0x1AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F0x2AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F0x3AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F0x0BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F0x1BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F0x2BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F0x3BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F0x0CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F0x1CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F0x2CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F0x3CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F0x0DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F0x1DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F0x2DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F0x3DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F0x0EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F0x1EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F0x2EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F0x3EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F0x0FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F0x1FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F0x2FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F0x3FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] 0x3F0x03PLL clock /4; PLL input: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0011 SUT=00]0x3F0x13PLL clock /4; PLL input: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms; [CKSEL=0011 SUT=01]0x3F0x23PLL clock /4; PLL input: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms; [CKSEL=0011 SUT=10]0x3F0x33PLL clock /4; PLL input: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=0011 SUT=11]0x3F0x01PLL clock /4; PLL input: Ext. Clock; Start-up time PWRDWN/RESET: 6K CK/14 CK + 0 ms; [CKSEL=0001 SUT=00]0x3F0x11PLL clock /4; PLL input: Ext. Clock; Start-up time PWRDWN/RESET: 6K CK/14 CK + 4 ms; [CKSEL=0001 SUT=01]0x3F0x21PLL clock /4; PLL input: Ext. Clock; Start-up time PWRDWN/RESET: 6K CK/14 CK + 64 ms; [CKSEL=0001 SUT=10]0x3F0x05PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0101 SUT=00]0x3F0x15PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0101 SUT=01]0x3F0x25PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms; [CKSEL=0101 SUT=10]0x3F0x35PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms; [CKSEL=0101 SUT=11]0x3F0x04Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0100 SUT=00]0x3F0x14Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0100 SUT=01]0x3F0x24Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms; [CKSEL=0100 SUT=10]0x3F0x34Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms; [CKSEL=0100 SUT=11]8RSTDISBLExternal Reset Disable1DWENDebugWIRE Enable1SPIENEnable Serial programming and Data Downloading0WDTONWatchdog timer always on1EESAVEEEPROM memory is preserved through chip erase1BOOTSZ1Select Boot Size0BOOTSZ0Select Boot Size0BOOTRSTSelect Reset Vector1130x800x00Reset Disabled (Enable PC6 as i/o pin); [RSTDISBL=0]0x400x00Debug Wire enable; [DWEN=0]0x200x00Serial program downloading (SPI) enabled; [SPIEN=0]0x100x00Watch-dog Timer always on; [WDTON=0]0x080x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x060x06Boot Flash section size=512 words Boot start address=$7E00; [BOOTSZ=11]0x060x04Boot Flash section size=1024 words Boot start address=$7C00; [BOOTSZ=10]0x060x02Boot Flash section size=2048 words Boot start address=$7800; [BOOTSZ=01]0x060x00Boot Flash section size=4096 words Boot start address=$7000; [BOOTSZ=00] ; default value0x010x00Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]6PSCRBPSC Reset Behavior1PSCRVAPSC Outputs xA Reset Value1PSCRVBPSC Outputs xB Reset Value1BODLEVEL2Brown-out Detector Trigger Level0BODLEVEL1Brown-out Detector Trigger Level0BODLEVEL0Brown-out Detector Trigger Level1110x200x00PSC Reset Behavior; [PSCRB=1]0x100x00PSC Module A Reset Value; [PSCARV=1]0x080x00PSC Module B Reset Value; [PSCBRV=1]0x070x07Brown-out detection disabled; [BODLEVEL=111]0x070x06Brown-out detection level at VCC=4.5 V; [BODLEVEL=110]0x070x05Brown-out detection level at VCC=2.7 V; [BODLEVEL=101]0x070x04Brown-out detection level at VCC=4.3 V; [BODLEVEL=100]0x070x03Brown-out detection level at VCC=4.4 V; [BODLEVEL=011]0x070x02Brown-out detection level at VCC=4.2 V; [BODLEVEL=010]0x070x01Brown-out detection level at VCC=2.8 V; [BODLEVEL=001]0x070x00Brown-out detection level at VCC=2.6 V; [BODLEVEL=000] [PORTB:PORTC:PORTD:CAN:ANALOG_COMPARATOR:DA_CONVERTER:CPU:PORTE:TIMER_COUNTER_0:TIMER_COUNTER_1:AD_CONVERTER:LINUART:SPI:WATCHDOG:EXTERNAL_INTERRUPT:EEPROM:PSC][PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register$05$25io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register$04$24io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.$03$23io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[PORTC:DDRC:PINC]io_port.bmpAVRSimIOPort.SimIOPortPORTCPort C Data Register$08$28io_port.bmpNPORTC7Port C Data Register bit 7RW0PORTC6Port C Data Register bit 6RW0PORTC5Port C Data Register bit 5RW0PORTC4Port C Data Register bit 4RW0PORTC3Port C Data Register bit 3RW0PORTC2Port C Data Register bit 2RW0PORTC1Port C Data Register bit 1RW0PORTC0Port C Data Register bit 0RW0DDRCPort C Data Direction Register$07$27io_flag.bmpNDDC7Port C Data Direction Register bit 7RW0DDC6Port C Data Direction Register bit 6RW0DDC5Port C Data Direction Register bit 5RW0DDC4Port C Data Direction Register bit 4RW0DDC3Port C Data Direction Register bit 3RW0DDC2Port C Data Direction Register bit 2RW0DDC1Port C Data Direction Register bit 1RW0DDC0Port C Data Direction Register bit 0RW0PINCPort C Input PinsThe Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read.$06$26io_port.bmpNPINC7Port C Input Pins bit 7R0PINC6Port C Input Pins bit 6R0PINC5Port C Input Pins bit 5R0PINC4Port C Input Pins bit 4R0PINC3Port C Input Pins bit 3R0PINC2Port C Input Pins bit 2R0PINC1Port C Input Pins bit 1R0PINC0Port C Input Pins bit 0R0[PORTD:DDRD:PIND]io_port.bmpAVRSimIOPort.SimIOPortPORTDPort D Data Register$0B$2Bio_port.bmpNPORTD7Port D Data Register bit 7RW0PORTD6Port D Data Register bit 6RW0PORTD5Port D Data Register bit 5RW0PORTD4Port D Data Register bit 4RW0PORTD3Port D Data Register bit 3RW0PORTD2Port D Data Register bit 2RW0PORTD1Port D Data Register bit 1RW0PORTD0Port D Data Register bit 0RW0DDRDPort D Data Direction Register$0A$2Aio_flag.bmpNDDD7Port D Data Direction Register bit 7RW0DDD6Port D Data Direction Register bit 6RW0DDD5Port D Data Direction Register bit 5RW0DDD4Port D Data Direction Register bit 4RW0DDD3Port D Data Direction Register bit 3RW0DDD2Port D Data Direction Register bit 2RW0DDD1Port D Data Direction Register bit 1RW0DDD0Port D Data Direction Register bit 0RW0PINDPort D Input PinsThe Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.$09$29io_port.bmpNPIND7Port D Input Pins bit 7R0PIND6Port D Input Pins bit 6R0PIND5Port D Input Pins bit 5R0PIND4Port D Input Pins bit 4R0PIND3Port D Input Pins bit 3R0PIND2Port D Input Pins bit 2R0PIND1Port D Input Pins bit 1R0PIND0Port D Input Pins bit 0R0[CANGCON:CANGSTA:CANGIT:CANGIE:CANEN2:CANEN1:CANIE2:CANIE1:CANSIT2:CANSIT1:CANBT1:CANBT2:CANBT3:CANTCON:CANTIML:CANTIMH:CANTTCL:CANTTCH:CANTEC:CANREC:CANHPMOB:CANPAGE:CANSTMOB:CANCDMOB:CANIDT4:CANIDT3:CANIDT2:CANIDT1:CANIDM4:CANIDM3:CANIDM2:CANIDM1:CANSTML:CANSTMH:CANMSG]io_com.bmpCAN InterfaceCANGCONCAN General Control RegisterNA0xD8register.bmpYABRQAbort RequestRW0OVRQOverload Frame RequestRW0TTCTime Trigger CommunicationRW0SYNTTCSynchronization of TTCRW0LISTENListening ModeRW0TESTTest ModeRW0ENASTBEnable / StandbyRW0SWRESSoftware Reset RequestRW0CANGSTACAN General Status RegisterNA0xD9io_flag.bmpYOVFGOverload Frame FlagR0TXBSYTransmitter BusyR0RXBSYReceiver BusyR0ENFGEnable FlagR0BOFFBus Off ModeR0ERRPError Passive ModeR0CANGITCAN General Interrupt Register FlagsNA0xDAio_flag.bmpYCANITGeneral Interrupt FlagR0BOFFITBus Off Interrupt FlagRW0OVRTIMOverrun CAN Timer FlagRW0BXOKBurst Receive Interrupt FlagRW0SERGStuff Error General FlagRW0CERGCRC Error General FlagRW0FERGForm Error General FlagRW0AERGAckknowledgement Error General FlagRW0CANGIECAN General Interrupt Enable RegisterNA0xDBregister.bmpYENITEnable all InterruptsRW0ENBOFFEnable Bus Off InterruptRW0ENRXEnable Receive InterruptRW0ENTXEnable Transmitt InterruptRW0ENERREnable MOb Error InterruptRW0ENBXEnable Burst Receive InterruptRW0ENERGEnable General Error InterruptRW0ENOVRTEnable CAN Timer Overrun InterruptRW0CANEN2Enable MOb Register 2NA0xDCregister.bmpYENMOB5Enable MOb 5R0ENMOB4Enable MOb 4R0ENMOB3Enable MOb 3R0ENMOB2Enable MOb 2R0ENMOB1Enable MOb 1R0ENMOB0Enable MOb 0R0CANEN1Enable MOb Register 1(empty)NA0xDDregister.bmpNCANIE2Enable Interrupt MOb Register 2NA0xDEregister.bmpYIEMOB5Interrupt Enable MOb 5RW0IEMOB4Interrupt Enable MOb 4RW0IEMOB3Interrupt Enable MOb 3RW0IEMOB2Interrupt Enable MOb 2RW0IEMOB1Interrupt Enable MOb 1RW0IEMOB0Interrupt Enable MOb 0RW0CANIE1Enable Interrupt MOb Register 1 (empty)NA0xDFregister.bmpNCANSIT2CAN Status Interrupt MOb Register 2NA0xE0io_flag.bmpYSIT5Status of Interrupt MOb 5R0SIT4Status of Interrupt MOb 4R0SIT3Status of Interrupt MOb 3R0SIT2Status of Interrupt MOb 2R0SIT1Status of Interrupt MOb 1R0SIT0Status of Interrupt MOb 0R0CANSIT1CAN Status Interrupt MOb Register 1 (empty)NA0xE1io_flag.bmpNCANBT1CAN Bit Timing Register 1NA0xE2register.bmpYBRP5Baud Rate Prescaler bit 5RW0BRP4Baud Rate Prescaler bit 4RW0BRP3Baud Rate Prescaler bit 3RW0BRP2Baud Rate Prescaler bit 2RW0BRP1Baud Rate Prescaler bit 1RW0BRP0Baud Rate Prescaler bit 0RW0CANBT2CAN Bit Timing Register 2NA0xE3register.bmpYSJW1Re-Sync Jump Width bit 1RW0SJW0Re-Sync Jump Width bit 0RW0PRS2Propagation Time Segment bit 2RW0PRS1Propagation Time Segment bit 1RW0PRS0Propagation Time Segment bit 0RW0CANBT3CAN Bit Timing Register 3NA0xE4register.bmpYPHS22Phase Segment 2 bit 2RW0PHS21Phase Segment 2 bit 1RW0PHS20Phase Segment 2 bit 0RW0PHS12Phase Segment 1 bit 2RW0PHS11Phase Segment 1 bit 1RW0PHS10Phase Segment 1 bit 0RW0SMPSample TypeRW0CANTCONTimer Control RegisterNA0xE5register.bmpNTPRSC7CAN Timer Prescaler bit 7RW0TPRSC6CAN Timer Prescaler bit 6RW0TPRSC5CAN Timer Prescaler bit 5RW0TPRSC4CAN Timer Prescaler bit 4RW0TPRSC3CAN Timer Prescaler bit 3RW0TPRSC2CAN Timer Prescaler bit 2RW0TPRSC1CAN Timer Prescaler bit 1RW0TPRSC0CAN Timer Prescaler bit 0RW0CANTIMLTimer Register LowNA0xE6register.bmpNCANTIM7CAN Timer Count bit 7R0CANTIM6CAN Timer Count bit 6R0CANTIM5CAN Timer Count bit 5R0CANTIM4CAN Timer Count bit 4R0CANTIM3CAN Timer Count bit 3R0CANTIM2CAN Timer Count bit 2R0CANTIM1CAN Timer Count bit 1R0CANTIM0CAN Timer Count bit 0R0CANTIMHTimer Register HighNA0xE7register.bmpNCANTIM15CAN Timer Count bit 15R0CANTIM14CAN Timer Count bit 14R0CANTIM13CAN Timer Count bit 13R0CANTIM12CAN Timer Count bit 12R0CANTIM11CAN Timer Count bit 11R0CANTIM10CAN Timer Count bit 10R0CANTIM9CAN Timer Count bit 9R0CANTIM8CAN Timer Count bit 8R0CANTTCLTTC Timer Register LowNA0xE8register.bmpNTIMTCC7TTC Timer Count bit 7R0TIMTCC6TTC Timer Count bit 6R0TIMTCC5TTC Timer Count bit 5R0TIMTCC4TTC Timer Count bit 4R0TIMTCC3TTC Timer Count bit 3R0TIMTCC2TTC Timer Count bit 2R0TIMTCC1TTC Timer Count bit 1R0TIMTCC0TTC Timer Count bit 0R0CANTTCHTTC Timer Register HighNA0xE9register.bmpNTIMTCC15TTC Timer Count bit 15R0TIMTCC14TTC Timer Count bit 14R0TIMTCC13TTC Timer Count bit 13R0TIMTCC12TTC Timer Count bit 12R0TIMTCC11TTC Timer Count bit 11R0TIMTCC10TTC Timer Count bit 10R0TIMTCC9TTC Timer Count bit 9R0TIMTCC8TTC Timer Count bit 8R0CANTECTransmit Error Counter RegisterNA0xEAregister.bmpNTEC7Transmit Error Count bit 7R0TEC6Transmit Error Count bit 6R0TEC5Transmit Error Count bit 5R0TEC4Transmit Error Count bit 4R0TEC3Transmit Error Count bit 3R0TEC2Transmit Error Count bit 2R0TEC1Transmit Error Count bit 1R0TEC0Transmit Error Count bit 0R0CANRECReceive Error Counter RegisterNA0xEBregister.bmpNREC7Receive Error Count bit 7R0REC6Receive Error Count bit 6R0REC5Receive Error Count bit 5R0REC4Receive Error Count bit 4R0REC3Receive Error Count bit 3R0REC2Receive Error Count bit 2R0REC1Receive Error Count bit 1R0REC0Receive Error Count bit 0R0CANHPMOBHighest Priority MOb RegisterNA0xECregister.bmpYHPMOB3Highest Priority MOb Number bit 3R1HPMOB2Highest Priority MOb Number bit 2R1HPMOB1Highest Priority MOb Number bit 1R1HPMOB0Highest Priority MOb Number bit 0R1CGP3CAN General Purpose bit 3RW0CGP2CAN General Purpose bit 2RW0CGP1CAN General Purpose bit 1RW0CGP0CAN General Purpose bit 0RW0CANPAGEPage MOb RegisterNA$EDregister.bmpYMOBNB3MOb Number bit 3RW0MOBNB2MOb Number bit 2RW0MOBNB1MOb Number bit 1RW0MOBNB0MOb Number bit 0RW0AINCMOb Data Buffer Auto Increment (Active Low)RW0INDX2Data Buffer Index bit 2RW0INDX1Data Buffer Index bit 1RW0INDX0Data Buffer Index bit 0RW0CANSTMOBMOb Status RegisterNA$EEio_flag.bmpYDLCWData Length Code Warning on MObRWXTXOKTransmit OK on MObRWXRXOKReceive OK on MObRWXBERRBit Error on MObRWXSERRStuff Error on MObRWXCERRCRC Error on MObRWXFERRForm Error on MObRWXAERRAckknowledgement Error on MObRWXCANCDMOBMOb Control and DLC RegisterNA$EFregister.bmpYCONMOB1MOb Config bit 1RWXCONMOB0MOb Config bit 0RWXRPLVReply ValidRWXIDEIdentifier ExtensionRWXDLC3Data Length Code bit 3RWXDLC2Data Length Code bit 2RWXDLC1Data Length Code bit 1RWXDLC0Data Length Code bit 0RWXCANIDT4Identifier Tag Register 4NA$F0register.bmpYIDT4RWXIDT3RWXIDT2RWXIDT1RWXIDT0RWXRTRTAGRWXRB1TAGRWXRB0TAGRWXCANIDT3Identifier Tag Register 3NA$F1register.bmpNIDT12RWXIDT11RWXIDT10RWXIDT9RWXIDT8RWXIDT7RWXIDT6RWXIDT5RWXCANIDT2Identifier Tag Register 2NA$F2register.bmpNIDT20RWXIDT19RWXIDT18RWXIDT17RWXIDT16RWXIDT15RWXIDT14RWXIDT13RWXCANIDT1Identifier Tag Register 1NA$F3register.bmpNIDT28RWXIDT27RWXIDT26RWXIDT25RWXIDT24RWXIDT23RWXIDT22RWXIDT21RWXCANIDM4Identifier Mask Register 4NA$F4register.bmpNIDMSK4RWXIDMSK3RWXIDMSK2RWXIDMSK1RWXIDMSK0RW0RTRMSKRWXIDEMSKRWXCANIDM3Identifier Mask Register 3NA$F5register.bmpNIDMSK12RWXIDMSK11RWXIDMSK10RWXIDMSK9RWXIDMSK8RWXIDMSK7RWXIDMSK6RWXIDMSK5RWXCANIDM2Identifier Mask Register 2NA$F6register.bmpNIDMSK20RWXIDMSK19RWXIDMSK18RWXIDMSK17RWXIDMSK16RWXIDMSK15RWXIDMSK14RWXIDMSK13RWXCANIDM1Identifier Mask Register 1NA$F7register.bmpNIDMSK28RWXIDMSK27RWXIDMSK26RWXIDMSK25RWXIDMSK24RWXIDMSK23RWXIDMSK22RWXIDMSK21RWXCANSTMLTime Stamp Register LowNA$F8register.bmpNTIMSTM7CAN Timer Count bit 7RWXTIMSTM6CAN Timer Count bit 6RWXTIMSTM5CAN Timer Count bit 5RWXTIMSTM4CAN Timer Count bit 4RWXTIMSTM3CAN Timer Count bit 3RWXTIMSTM2CAN Timer Count bit 2RWXTIMSTM1CAN Timer Count bit 1RWXTIMSTM0CAN Timer Count bit 0RWXCANSTMHTime Stamp Register HighNA$F9register.bmpNTIMSTM15CAN Timer Count bit 15RWXTIMSTM14CAN Timer Count bit 14RWXTIMSTM13CAN Timer Count bit 13RWXTIMSTM12CAN Timer Count bit 12RWXTIMSTM11CAN Timer Count bit 11RWXTIMSTM10CAN Timer Count bit 10RWXTIMSTM9CAN Timer Count bit 9RWXTIMSTM8CAN Timer Count bit 0RWXCANMSGMessage Data RegisterNA$FAregister.bmpNMSG7Message Data bit 7RWXMSG6Message Data bit 6RWXMSG5Message Data bit 5RWXMSG4Message Data bit 4RWXMSG3Message Data bit 3RWXMSG2Message Data bit 2RWXMSG1Message Data bit 1RWXMSG0Message Data bit 0RWX[AC0CON:AC1CON:AC2CON:AC3CON:ACSR]io_analo.bmpAlgComp_14AC0CONAnalog Comparator 0 Control RegisterNA$94io_flag.bmpYAC0ENAnalog Comparator 0 Enable BitRW0AC0IEAnalog Comparator 0 Interrupt Enable BitRW0AC0IS1Analog Comparator 0 Interrupt Select Bit 1RW0AC0IS0Analog Comparator 0 Interrupt Select Bit 0RW0ACCKSELAnalog Comparator Clock SelectRW0AC0M2Analog Comparator 0 Multiplexer RegisterRW0AC0M1Analog Comparator 0 Multiplexer RegsiterRW0AC0M0Analog Comparator 0 Multiplexer RegisterRW0AC1CONAnalog Comparator 1 Control RegisterNA$95io_flag.bmpYAC1ENAnalog Comparator 1 Enable BitRW0AC1IEAnalog Comparator 1 Interrupt Enable BitRW0AC1IS1Analog Comparator 1 Interrupt Select BitRW0AC1IS0Analog Comparator 1 Interrupt Select BitRWANALOG_COMP_INTERRUPT0AC1ICEAnalog Comparator 1 Interrupt Capture Enable BitRW0AC1M2Analog Comparator 1 Multiplexer RegisterRW0AC1M1Analog Comparator 1 Multiplexer RegsiterRW0AC1M0Analog Comparator 1 Multiplexer RegisterRW0AC2CONAnalog Comparator 2 Control RegisterNA$96io_flag.bmpYAC2ENAnalog Comparator 2 Enable BitRW0AC2IEAnalog Comparator 2 Interrupt Enable BitRW0AC2IS1Analog Comparator 2 Interrupt Select BitRW0AC2IS0Analog Comparator 2 Interrupt Select BitRWANALOG_COMP_INTERRUPT0AC2M2Analog Comparator 2 Multiplexer RegisterRW0AC2M1Analog Comparator 2 Multiplexer RegsiterRW0AC2M0Analog Comparator 2 Multiplexer RegisterRW0AC3CONAnalog Comparator 3 Control RegisterNA$97io_flag.bmpYAC3ENAnalog Comparator 3 Enable BitRW0AC3IEAnalog Comparator 3 Interrupt Enable BitRW0AC3IS1Analog Comparator 3 Interrupt Select BitRW0AC3IS0Analog Comparator 3 Interrupt Select BitRWANALOG_COMP_INTERRUPT0AC3M2Analog Comparator 3 Multiplexer RegisterRW0AC3M1Analog Comparator 3 Multiplexer RegsiterRW0AC3M0Analog Comparator 3 Multiplexer RegisterRW0ACSRAnalog Comparator Status Register$30$50io_flag.bmpYAC3IFAnalog Comparator 3 Interrupt Flag BitRW0AC2IFAnalog Comparator 2 Interrupt Flag BitRW0AC1IFAnalog Comparator 1 Interrupt Flag BitRW0AC0IFAnalog Comparator 0 Interrupt Flag BitRW0AC3OAnalog Comparator 3 Output BitRW0AC2OAnalog Comparator 2 Output BitRW0AC1OAnalog Comparator 1 Output BitRW0AC0OAnalog Comparator 0 Output BitRW0[DACH:DACL:DACON]((IF DACON.DALA = 0) LINK [DACH(1:0):DACL(7:0)]); (IF DACON.DALA = 1) LINK [DACH(7:0):DACL(7:6)]);io_analo.bmpDigital to Analog ConverterDACHDAC Data Register High ByteNA$92io_analo.bmpYDACH7DAC Data Register High Byte Bit 7RW0DACH6DAC Data Register High Byte Bit 6RW0DACH5DAC Data Register High Byte Bit 5RW0DACH4DAC Data Register High Byte Bit 4RW0DACH3DAC Data Register High Byte Bit 3RW0DACH2DAC Data Register High Byte Bit 2RW0DACH1DAC Data Register High Byte Bit 1RW0DACH0DAC Data Register High Byte Bit 0RW0DACLDAC Data Register Low ByteNA$91io_analo.bmpYDACL7DAC Data Register Low Byte Bit 7RW0DACL6DAC Data Register Low Byte Bit 6RW0DACL5DAC Data Register Low Byte Bit 5RW0DACL4DAC Data Register Low Byte Bit 4RW0DACL3DAC Data Register Low Byte Bit 3RW0DACL2DAC Data Register Low Byte Bit 2RW0DACL1DAC Data Register Low Byte Bit 1RW0DACL0DAC Data Register Low Byte Bit 0RW0DACONDAC Control RegisterNA$90io_analo.bmpYDAATEDAC Auto Trigger Enable BitRW0DATS2DAC Trigger Selection Bit 2RW0DATS1DAC Trigger Selection Bit 1RW0DATS0DAC Trigger Selection Bit 0RWANALIG_DAC_AUTO_TRIGGER0DALADAC Left AdjustRW0DAENDAC Enable BitRW0[SPMCSR:SREG:SPH:SPL:MCUCR:MCUSR:OSCCAL:CLKPR:SMCR:GPIOR2:GPIOR1:GPIOR0:PLLCSR:PRR]
[SPH:SPL]
io_cpu.bmpSPMCSRSPMCRStore Program Memory Control RegisterThe Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.$37$57io_flag.bmpYSPMIESPM Interrupt EnableWhen the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.RW0RWWSBASBRead While Write Section BusyWhen a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.R0SIGRDSignature Row ReadIf this bit is written to one at the same time as SPMEN, the next LPM instruction whithin three clock cycles will read a byte from the signature row into the destination register.RW0RWWSREASRERead While Write section read enableWhen programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be loRW0BLBSETBoot Lock Bit SetIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for detailsRW0PGWRTPage WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0PGERSPage EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0SPMENStore Program Memory EnableThis bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effecRW0SREGStatus Register$3F$5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPHStack Pointer HighThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R$3E$5Eio_sph.bmpNSP15Stack pointer bit 15RW0SP14Stack pointer bit 14RW0SP13Stack pointer bit 13RW0SP12Stack pointer bit 12RW0SP11Stack pointer bit 11RW0SP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW0SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt $3D$5Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35$55io_flag.bmpYSPIPSSPI Pin SelectRW0PUDPull-up disableWhen this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). RW0IVSELInterrupt Vector SelectWhen the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. RW0IVCEInterrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts. RW0MCUSRMCU Status RegisterThe MCU Status Register provides information on which reset source caused an MCU reset.$34$54io_flag.bmpYWDRFWatchdog Reset FlagThis bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0BORFBrown-out Reset FlagThis bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0EXTRFExternal Reset FlagThis bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0PORFPower-on reset flagThis bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.R/W0OSCCALOscillator Calibration ValueWriting the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14NA$66io_cpu.bmpNCAL6Oscillator Calibration Value Bit6R/W0CAL5Oscillator Calibration Value Bit5R/W0CAL4Oscillator Calibration Value Bit4R/W0CAL3Oscillator Calibration Value Bit3R/W0CAL2Oscillator Calibration Value Bit2R/W0CAL1Oscillator Calibration Value Bit1R/W0CAL0Oscillator Calibration Value Bit0R/W0CLKPRNA$61io_cpu.bmpYCLKPCECLKPS3CPU_CLK_PRESCALE_4_BITS_SMALLCLKPS2CLKPS1CLKPS0SMCRSleep Mode Control RegisterThe Sleep Mode Control Register contains control bits for power management.$33$53io_cpu.bmpYSM2Sleep Mode Select bit 2These bits select between the five available sleep modes.RW0SM1Sleep Mode Select bit 1These bits select between the five available sleep modes.RW0SM0Sleep Mode Select bit 0These bits select between the five available sleep modes.RWCPU_SLEEP_MODE_3BITS40SESleep EnableThe SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.ToRW0GPIOR2General Purpose IO Register 2$1A$3Aio_cpu.bmpYGPIOR27General Purpose IO Register 2 bit 7RW0GPIOR26General Purpose IO Register 2 bit 6RW0GPIOR25General Purpose IO Register 2 bit 5RW0GPIOR24General Purpose IO Register 2 bit 4RW0GPIOR23General Purpose IO Register 2 bit 3RW0GPIOR22General Purpose IO Register 2 bit 2RW0GPIOR21General Purpose IO Register 2 bit 1RW0GPIOR20General Purpose IO Register 2 bit 0RW0GPIOR1General Purpose IO Register 1$19$39io_cpu.bmpYGPIOR17General Purpose IO Register 1 bit 7RW0GPIOR16General Purpose IO Register 1 bit 6RW0GPIOR15General Purpose IO Register 1 bit 5RW0GPIOR14General Purpose IO Register 1 bit 4RW0GPIOR13General Purpose IO Register 1 bit 3RW0GPIOR12General Purpose IO Register 1 bit 2RW0GPIOR11General Purpose IO Register 1 bit 1RW0GPIOR10General Purpose IO Register 1 bit 0RW0GPIOR0General Purpose IO Register 0$1E$3Eio_cpu.bmpYGPIOR07General Purpose IO Register 0 bit 7RW0GPIOR06General Purpose IO Register 0 bit 6RW0GPIOR05General Purpose IO Register 0 bit 5RW0GPIOR04General Purpose IO Register 0 bit 4RW0GPIOR03General Purpose IO Register 0 bit 3RW0GPIOR02General Purpose IO Register 0 bit 2RW0GPIOR01General Purpose IO Register 0 bit 1RW0GPIOR00General Purpose IO Register 0 bit 0RW0PLLCSRPLL Control And Status Register$29$49io_sreg.bmpYPLLFPLL FactorThe PLLF bit is used to select the division factor of the PLL.RW0PLLEPLL EnableRW0PLOCKPLL Lock DetectorR0PRRPower Reduction RegisterNA$64io_cpu.bmpYPRCANPower Reduction CANR/W0PRPSCPower Reduction PSCR/W0PRTIM1Power Reduction Timer/Counter1R/W0PRTIM0Power Reduction Timer/Counter0R/W0PRSPIPower Reduction Serial Peripheral InterfaceR/W0PRLINPower Reduction LIN UARTR/W0PRADCPower Reduction ADCR/W0[PORTE:DDRE:PINE]io_port.bmpAVRSimIOPort.SimIOPortPORTEPort E Data Register$0E$2Eio_port.bmpNPORTE2RW0PORTE1RW0PORTE0RW0DDREPort E Data Direction Register$0D$2Dio_flag.bmpNDDE2RW0DDE1RW0DDE0RW0PINEPort E Input Pins$0C$2Cio_port.bmpNPINE2R0PINE1R0PINE0R0[TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR]io_timer.bmpAt8pwm0_12TIMSK0Timer/Counter0 Interrupt Mask RegisterNA$6Eio_flag.bmpYOCIE0BTimer/Counter0 Output Compare Match B Interrupt EnableRW0OCIE0ATimer/Counter0 Output Compare Match A Interrupt EnableRW0TOIE0Timer/Counter0 Overflow Interrupt EnableRW0TIFR0Timer/Counter0 Interrupt Flag register$15$35io_flag.bmpYOCF0BTimer/Counter0 Output Compare Flag 0BRW0OCF0ATimer/Counter0 Output Compare Flag 0ARW0TOV0Timer/Counter0 Overflow FlagRW0TCCR0ATimer/Counter Control Register A$24$44io_flag.bmpYCOM0A1Compare Output Mode, Phase Correct PWM ModeRW0COM0A0Compare Output Mode, Phase Correct PWM ModeRW0COM0B1Compare Output Mode, Fast PWmW0COM0B0Compare Output Mode, Fast PWmRW0WGM01Waveform Generation ModeRW0WGM00Waveform Generation ModeRW0TCCR0BTimer/Counter Control Register B$25$45io_flag.bmpYFOC0AForce Output Compare AW0FOC0BForce Output Compare BW0WGM02RW0CS02Clock SelectRW0CS01Clock SelectRW0CS00Clock SelectRWCLK_SEL_3BIT_EXT0TCNT0Timer/Counter0The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.$26$46io_timer.bmpNTCNT0_7RW0TCNT0_6RW0TCNT0_5RW0TCNT0_4RW0TCNT0_3RW0TCNT0_2RW0TCNT0_1RW0TCNT0_0RW0OCR0ATimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$27$47io_timer.bmpNOCR0A_7RW0OCR0A_6RW0OCR0A_5RW0OCR0A_4RW0OCR0A_3RW0OCR0A_2RW0OCR0A_1RW0OCR0A_0RW0OCR0BTimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$28$48io_timer.bmpNOCR0B_7RW0OCR0B_6RW0OCR0B_5RW0OCR0B_4RW0OCR0B_3RW0OCR0B_2RW0OCR0B_1RW0OCR0B_0RW0GTCCRGeneral Timer/Counter Control Register$23$43io_flag.bmpYTSMTimer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneouslRW0ICPSEL1Timer1 Input Capture Selection BitRW0PSR10Prescaler Reset Timer/Counter1 and Timer/Counter0When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.RW0[TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L:GTCCR]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L]
io_timer.bmpt16pwm1_12.xmlTIMSK1Timer/Counter Interrupt Mask RegisterNA$6Fio_flag.bmpYICIE1Timer/Counter1 Input Capture Interrupt EnableWhen the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1BTimer/Counter1 Output CompareB Match Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE1ATimer/Counter1 Output CompareA Match Interrupt EnableWhen the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE1Timer/Counter1 Overflow Interrupt EnableWhen the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFR1Timer/Counter Interrupt Flag register$16$36io_flag.bmpYICF1Input Capture Flag 1The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW0OCF1BOutput Compare Flag 1BThe OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.RW0OCF1AOutput Compare Flag 1AThe OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW0TOV1Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.RW0TCCR1ATimer/Counter1 Control Register ANA$80io_flag.bmpYCOM1A1Compare Output Mode 1A, bit 1The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM1A0Comparet Ouput Mode 1A, bit 0The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM1B1Compare Output Mode 1B, bit 1The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM1B0Compare Output Mode 1B, bit 0The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0WGM11Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM10Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0TCCR1BTimer/Counter1 Control Register BNA$81io_flag.bmpYICNC1Input Capture 1 Noise CancelerWhen the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES1Input Capture 1 Edge SelectWhile the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.RW0WGM13Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM12Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0CS12Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS11Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS10Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RWCLK_SEL_3BIT_EXT0TCCR1CTimer/Counter1 Control Register CNA$82io_flag.bmpYFOC1ARW0FOC1BRW0TCNT1HTimer/Counter1 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rouNA$85io_timer.bmpNTCNT1H7Timer/Counter1 High Byte bit 7RW0TCNT1H6Timer/Counter1 High Byte bit 6RW0TCNT1H5Timer/Counter1 High Byte bit 5RW0TCNT1H4Timer/Counter1 High Byte bit 4RW0TCNT1H3Timer/Counter1 High Byte bit 3RW0TCNT1H2Timer/Counter1 High Byte bit 2RW0TCNT1H1Timer/Counter1 High Byte bit 1RW0TCNT1H0Timer/Counter1 High Byte bit 0RW0TCNT1LTimer/Counter1 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$84io_timer.bmpNTCNT1L7Timer/Counter1 Low Byte bit 7RW0TCNT1L6Timer/Counter1 Low Byte bit 6RW0TCNT1L5Timer/Counter1 Low Byte bit 5RW0TCNT1L4Timer/Counter1 Low Byte bit 4RW0TCNT1L3Timer/Counter1 Low Byte bit 3RW0TCNT1L2Timer/Counter1 Low Byte bit 2RW0TCNT1L1Timer/Counter1 Low Byte bit 1RW0TCNT1L0Timer/Counter1 Low Byte bit 0RW0OCR1AHTimer/Counter1 Output Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$89io_timer.bmpNOCR1AH7Timer/Counter1 Output Compare Register High Byte bit 7RW0OCR1AH6Timer/Counter1 Output Compare Register High Byte bit 6RW0OCR1AH5Timer/Counter1 Output Compare Register High Byte bit 5RW0OCR1AH4Timer/Counter1 Output Compare Register High Byte bit 4RW0OCR1AH3Timer/Counter1 Output Compare Register High Byte bit 3RW0OCR1AH2Timer/Counter1 Output Compare Register High Byte bit 2RW0OCR1AH1Timer/Counter1 Output Compare Register High Byte bit 1RW0OCR1AH0Timer/Counter1 Output Compare Register High Byte bit 0RW0OCR1ALTimer/Counter1 Output Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$88io_timer.bmpNOCR1AL7Timer/Counter1 Output Compare Register Low Byte Bit 7RW0OCR1AL6Timer/Counter1 Output Compare Register Low Byte Bit 6RW0OCR1AL5Timer/Counter1 Output Compare Register Low Byte Bit 5RW0OCR1AL4Timer/Counter1 Output Compare Register Low Byte Bit 4RW0OCR1AL3Timer/Counter1 Output Compare Register Low Byte Bit 3RW0OCR1AL2Timer/Counter1 Output Compare Register Low Byte Bit 2RW0OCR1AL1Timer/Counter1 Output Compare Register Low Byte Bit 1RW0OCR1AL0Timer/Counter1 Output Compare Register Low Byte Bit 0RW0OCR1BHTimer/Counter1 Output Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt roNA$8Bio_timer.bmpNOCR1BH7Timer/Counter1 Output Compare Register High Byte bit 7RW0OCR1BH6Timer/Counter1 Output Compare Register High Byte bit 6RW0OCR1BH5Timer/Counter1 Output Compare Register High Byte bit 5RW0OCR1BH4Timer/Counter1 Output Compare Register High Byte bit 4RW0OCR1BH3Timer/Counter1 Output Compare Register High Byte bit 3RW0OCR1BH2Timer/Counter1 Output Compare Register High Byte bit 2RW0OCR1BH1Timer/Counter1 Output Compare Register High Byte bit 1RW0OCR1BH0Timer/Counter1 Output Compare Register High Byte bit 0RW0OCR1BLTimer/Counter1 Output Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$8Aio_timer.bmpNOCR1BL7Timer/Counter1 Output Compare Register Low Byte bit 7R0OCR1BL6Timer/Counter1 Output Compare Register Low Byte bit 6RW0OCR1BL5Timer/Counter1 Output Compare Register Low Byte bit 5RW0OCR1BL4Timer/Counter1 Output Compare Register Low Byte bit 4RW0OCR1BL3Timer/Counter1 Output Compare Register Low Byte bit 3RW0OCR1BL2Timer/Counter1 Output Compare Register Low Byte bit 2RW0OCR1BL1Timer/Counter1 Output Compare Register Low Byte bit 1RW0OCR1BL0Timer/Counter1 Output Compare Register Low Byte bit 0RW0ICR1HTimer/Counter1 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruptNA$87io_timer.bmpNICR1H7Timer/Counter1 Input Capture Register High Byte bit 7RW0ICR1H6Timer/Counter1 Input Capture Register High Byte bit 6R0ICR1H5Timer/Counter1 Input Capture Register High Byte bit 5R0ICR1H4Timer/Counter1 Input Capture Register High Byte bit 4R0ICR1H3Timer/Counter1 Input Capture Register High Byte bit 3R0ICR1H2Timer/Counter1 Input Capture Register High Byte bit 2R0ICR1H1Timer/Counter1 Input Capture Register High Byte bit 1R0ICR1H0Timer/Counter1 Input Capture Register High Byte bit 0R0ICR1LTimer/Counter1 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interNA$86io_timer.bmpNICR1L7Timer/Counter1 Input Capture Register Low Byte bit 7R0ICR1L6Timer/Counter1 Input Capture Register Low Byte bit 6R0ICR1L5Timer/Counter1 Input Capture Register Low Byte bit 5R0ICR1L4Timer/Counter1 Input Capture Register Low Byte bit 4R0ICR1L3Timer/Counter1 Input Capture Register Low Byte bit 3R0ICR1L2Timer/Counter1 Input Capture Register Low Byte bit 2R0ICR1L1Timer/Counter1 Input Capture Register Low Byte bit 1R0ICR1L0Timer/Counter1 Input Capture Register Low Byte bit 0R0GTCCRGeneral Timer/Counter Control Register$23$43io_flag.bmpYTSMTimer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousRW0PSRSYNCPrescaler Reset Timer/Counter1 and Timer/Counter0When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.RW0[ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0:DIDR1:AMP0CSR:AMP1CSR:AMP2CSR]((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);io_analo.bmpAD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode NoiADMUXThe ADC multiplexer Selection RegisterThese bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.NA$7Cio_analo.bmpYREFS1Reference Selection Bit 1These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0REFS0Reference Selection Bit 0These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RWANALOG_ADC_V_REF20ADLARLeft Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW0MUX4Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX3Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADCSRAThe ADC Control and Status registerNA$7Aio_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effectRW0ADATEADC Auto Trigger EnableWhen this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjNA$79io_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right aNA$78io_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0ADCSRBADC Control and Status Register BNA$7Bio_analo.bmpYADHSMADC High Speed ModeRW0ISRCENCurrent Source EnableRW0AREFENAnalog Reference pin EnableRW0ADTS3ADC Auto Trigger Source 3RW0ADTS2ADC Auto Trigger Source 2RW0ADTS1ADC Auto Trigger Source 1RW0ADTS0ADC Auto Trigger Source 0RWANALIG_ADC_AUTO_TRIGGER_4BITS0DIDR0Digital Input Disable Register 0NA$7Eio_analo.bmpYADC7DADC7 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC6DADC6 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC5DADC5 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC4DADC4 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC3DADC3 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC2DADC2 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC1DADC1 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC0DADC0 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0DIDR1Digital Input Disable Register 0NA$7Fio_analo.bmpYAMP2PDAMP2P Pin Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding Amplifier pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ACMP0DACMP0 Pin Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding Analog Comparator pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0AMP0PDAMP0P Pin Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding Amplifier pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0AMP0NDAMP0N Pin Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding Amplifier pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC10DADC10 Pin Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC9DADC9 Pin Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0ADC8DADC8 Pin Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0AMP0CSRNA$75io_analo.bmpYAMP0ENRW0AMP0ISRW0AMP0G1RW0AMP0G0RW0AMPCMP0Amplifier 0 - Comparator 0 ConnectionRW0AMP0TS2RW0AMP0TS1RW0AMP0TS0RW0AMP1CSRNA$76io_analo.bmpYAMP1ENRW0AMP1ISRW0AMP1G1RW0AMP1G0RW0AMPCMP1Amplifier 1 - Comparator 1 ConnectionRW0AMP1TS2RW0AMP1TS1RW0AMP1TS0RW0AMP2CSRNA$77io_analo.bmpYAMP2ENRW0AMP2ISRW0AMP2G1RW0AMP2G0RW0AMPCMP2Amplifier 2 - Comparator 2 ConnectionRW0AMP2TS2RW0AMP2TS1RW0AMP2TS0RW0[LINCR:LINSIR:LINENIR:LINERR:LINBTR:LINBRRL:LINBRRH:LINDLR:LINIDR:LINSEL:LINDAT]io_com.bmpLIN or UART InterfaceLINCRLIN Control RegisterNA0xC8io_analo.bmpYLSWRESSoftware ResetRW0LIN13LIN StandardRW0LCONF1LIN Configuration bit 1RW0LCONF0LIN Configuration bit 0RW0LENALIN or UART EnableRW0LCMD2LIN Command and Mode bit 2RW0LCMD1LIN Command and Mode bit 1RW0LCMD0LIN Command and Mode bit 0RW0LINSIRLIN Status and Interrupt RegisterNA0xC9io_flag.bmpYLIDST2Identifier Status bit 2R0LIDST1Identifier Status bit 1R0LIDST0Identifier Status bit 0R0LBUSYBusy SignalR0LERRError InterruptRW0LIDOKIdentifier InterruptRW0LTXOKTransmit Performed InterruptRW0LRXOKReceive Performed InterruptRW0LINENIRLIN Enable Interrupt RegisterNA0xCAio_analo.bmpYLENERREnable Error InterruptRW0LENIDOKEnable Identifier InterruptRW0LENTXOKEnable Transmit Performed InterruptRW0LENRXOKEnable Receive Performed InterruptRW0LINERRLIN Error RegisterNA0xCBio_flag.bmpYLABORTAbort FlagR0LTOERRFrame Time Out Error FlagR0LOVERROverrun Error FlagR0LFERRFraming Error FlagR0LSERRSynchronization Error FlagR0LPERRParity Error FlagR0LCERRChecksum Error FlagR0LBERRBit Error FlagR0LINBTRLIN Bit Timing RegisterNA0xCCio_flag.bmpYLDISRDisable Bit Timing ResynchronizationRW0LBT5LIN Bit Timing bit 5RW1LBT4LIN Bit Timing bit 4RW0LBT3LIN Bit Timing bit 3RW0LBT2LIN Bit Timing bit 2RW0LBT1LIN Bit Timing bit 1RW0LBT0LIN Bit Timing bit 0RW0LINBRRLLIN Baud Rate Low RegisterNA0xCDio_timer.bmpYLDIV7RW0LDIV6RW0LDIV5RW0LDIV4RW0LDIV3RW0LDIV2RW0LDIV1RW0LDIV0RW0LINBRRHLIN Baud Rate High RegisterNA0xCEio_timer.bmpYLDIV11RW0LDIV10RW0LDIV9RW0LDIV8RW0LINDLRLIN Data Length RegisterNA0xCFio_com.bmpYLTXDL3LIN Transmit Data Length bit 3RW0LTXDL2LIN Transmit Data Length bit 2RW0LTXDL1LIN Transmit Data Length bit 1RW0LTXDL0LIN Transmit Data Length bit 0RW0LRXDL3LIN Receive Data Length bit 3RW0LRXDL2LIN Receive Data Length bit 2RW0LRXDL1LIN Receive Data Length bit 1RW0LRXDL0LIN Receive Data Length bit 0RW0LINIDRLIN Identifier RegisterNA0xD0io_com.bmpYLP1Parity bit 1R0LP0Parity bit 0R0LID5Identifier bit 5 or Data Length bit 1RW0LID4Identifier bit 4 or Data Length bit 0RW0LID3Identifier bit 3RW0LID2Identifier bit 2RW0LID1Identifier bit 1RW0LID0Identifier bit 0RW0LINSELLIN Data Buffer Selection RegisterNA0xD1io_com.bmpYLAINCAuto Increment of Data Buffer Index (Active Low)RW0LINDX2FIFO LIN Data Buffer Index bit 2RW0LINDX1FIFO LIN Data Buffer Index bit 1RW0LINDX0FIFO LIN Data Buffer Index bit 0RW0LINDATLIN Data RegisterNA0xD2io_com.bmpYLDATA7RW0LDATA6RW0LDATA5RW0LDATA4RW0LDATA3RW0LDATA2RW0LDATA1RW0LDATA0RW0[SPDR:SPSR:SPCR]io_com.bmpThe Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)SPCRSPI Control Register$2C$4Cio_flag.bmpYSPIESPI Interrupt EnableThis bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.RW0SPESPI EnableWhen the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.RW0DORDData OrderWhen the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.RW0MSTRMaster/Slave SelectThis bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.RW0CPOLClock polarityWhen this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.RW0CPHAClock PhaseRefer to Figure 36 or Figure 37 for the functionality of this bit.RW0SPR1SPI Clock Rate Select 1These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RW0SPR0SPI Clock Rate Select 0These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RWCOMM_SCK_RATE_3BIT0SPSRSPI Status Register$2D$4Dio_flag.bmpYSPIFSPI Interrupt FlagWhen a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).R0WCOLWrite Collision FlagThe WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.R0SPI2XDouble SPI Speed BitWhen this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading. RW0SPDRSPI Data RegisterThe SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.$2E$4Eio_com.bmpNSPDR7SPI Data Register bit 7RWXSPDR6SPI Data Register bit 6RWXSPDR5SPI Data Register bit 5RWXSPDR4SPI Data Register bit 4RWXSPDR3SPI Data Register bit 3RWXSPDR2SPI Data Register bit 2RWXSPDR1SPI Data Register bit 1R0SPDR0SPI Data Register bit 0R0[WDTCSR]io_watch.bmpWDTCSRWatchdog Timer Control RegisterNA$60io_flag.bmpYWDIFWatchdog Timeout Interrupt FlagRW0WDIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2WDOG_TIMER_PRESCALE_4BITSRW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[EICRA:EIMSK:EIFR:PCICR:PCMSK3:PCMSK2:PCMSK1:PCMSK0:PCIFR]io_ext.bmpThe External Interrupts are triggered by the INT3:0 pins or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT23..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK3, PCMSK2, PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT26..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.EICRAExternal Interrupt Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.NA$69io_flag.bmpYISC31External Interrupt Sense Control BitRW0ISC30External Interrupt Sense Control BitRWINTERRUPT_SENSE_CONTROL0ISC21External Interrupt Sense Control BitRW0ISC20External Interrupt Sense Control BitRWINTERRUPT_SENSE_CONTROL0ISC11External Interrupt Sense Control 1 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC10External Interrupt Sense Control 1 Bit 0The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RWINTERRUPT_SENSE_CONTROL0ISC01External Interrupt Sense Control 0 Bit 1 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC00External Interrupt Sense Control 0 Bit 0The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RWINTERRUPT_SENSE_CONTROL0EIMSKExternal Interrupt Mask Register$1D$3Dio_flag.bmpYINT3External Interrupt Request 3 EnableWhen the INT3 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control3 bits 1/0 (ISC21 and ISC20)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT3 pin or level sensed.Activity on the pin will cause an interrupt request even if INT3 is configured as an output.The corresponding interrupt of External Interrupt Request 3 is executed from the INT3 interruRW0INT2External Interrupt Request 2 EnableWhen the INT2 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control2 bits 1/0 (ISC21 and ISC20)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT2 pin or level sensed.Activity on the pin will cause an interrupt request even if INT2 is configured as an output.The corresponding interrupt of External Interrupt Request 2 is executed from the INT2 interruptRW0INT1External Interrupt Request 1 EnableWhen the INT1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vectoRW0INT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.Activity on the pin will cause an interrupt request even if INT0 is configured as an output.The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector. RW0EIFRExternal Interrupt Flag Register$1C$3Cio_flag.bmpYINTF3External Interrupt Flag 3When an edge or logic change on the INT3 pin triggers an interrupt request,INTF3 becomes set (one).If the I-bit in SREG and the INT3 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT3 is configured as a level interrupt. RW0INTF2External Interrupt Flag 2When an edge or logic change on the INT2 pin triggers an interrupt request,INTF2 becomes set (one).If the I-bit in SREG and the INT2 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT2 is configured as a level interrupt. RW0INTF1External Interrupt Flag 1When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW0INTF0External Interrupt Flag 0When an edge or logic change on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW0PCICRPin Change Interrupt Control RegisterNA$68io_cpu.bmpYPCIE3Pin Change Interrupt Enable 3R/W0PCIE2Pin Change Interrupt Enable 2R/W0PCIE1Pin Change Interrupt Enable 1R/W0PCIE0Pin Change Interrupt Enable 0R/W0PCMSK3Pin Change Mask Register 3Each PCINT26..24 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT26..24 is set and the PCIE3 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT26..24 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA$6Dio_flag.bmpYPCINT26Pin Change Enable Mask 26RW0PCINT25Pin Change Enable Mask 25RWPCINT24Pin Change Enable Mask 24RW0PCMSK2Pin Change Mask Register 2Each PCINT23..16 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT23..16 is set and the PCIE2 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT23..16 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA$6Cio_flag.bmpYPCINT23Pin Change Enable Mask 23RW0PCINT22Pin Change Enable Mask 22RW0PCINT21Pin Change Enable Mask 21RW0PCINT20Pin Change Enable Mask 20RW0PCINT19Pin Change Enable Mask 19RW0PCINT18Pin Change Enable Mask 18RW0PCINT17Pin Change Enable Mask 17RW0PCINT16Pin Change Enable Mask 16RW0PCMSK1Pin Change Mask Register 1Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is set and the PCIE1 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA$6Bio_flag.bmpYPCINT15Pin Change Enable Mask 15RW0PCINT14Pin Change Enable Mask 14RW0PCINT13Pin Change Enable Mask 13RW0PCINT12Pin Change Enable Mask 12RW0PCINT11Pin Change Enable Mask 11RW0PCINT10Pin Change Enable Mask 10RW0PCINT9Pin Change Enable Mask 9RW0PCINT8Pin Change Enable Mask 8RW0PCMSK0Pin Change Mask Register 0Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT7..0 is set and the PCIE0 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT7..0 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA$6Aio_flag.bmpYPCINT7Pin Change Enable Mask 7RW0PCINT6Pin Change Enable Mask 6RW0PCINT5Pin Change Enable Mask 5RW0PCINT4Pin Change Enable Mask 4RW0PCINT3Pin Change Enable Mask 3RW0PCINT2Pin Change Enable Mask 2RW0PCINT1Pin Change Enable Mask 1RW0PCINT0Pin Change Enable Mask 0RW0PCIFRPin Change Interrupt Flag Register$1B$3Bio_flag.bmpYPCIF3Pin Change Interrupt Flag 3When a logic change on any PCINT26..24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCIF2Pin Change Interrupt Flag 2When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCIF1Pin Change Interrupt Flag 1When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCIF0Pin Change Interrupt Flag 0When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0[EEARH:EEARL:EEDR:EECR]
[EEARH:EEARL]
io_cpu.bmpEEPROM_10_ENH.xmlEnhancement of EEPROM_10.xml (EEPM[1:0] in EECR)EEARHEEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction$22$42io_cpu.bmpNEEAR10EEPROM Read/Write Access bit 10RW0EEAR9EEPROM Read/Write Access bit 9RW0EEAR8EEPROM Read/Write Access bit 8RW0EEARLEEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction$21$41io_cpu.bmpNEEAR7EEPROM Read/Write Access bit 7RW0EEAR6EEPROM Read/Write Access bit 6RW0EEAR5EEPROM Read/Write Access bit 5RW0EEAR4EEPROM Read/Write Access bit 4RW0EEAR3EEPROM Read/Write Access bit 3RW0EEAR2EEPROM Read/Write Access bit 2RW0EEAR1EEPROM Read/Write Access bit 1RW0EEAR0EEPROM Read/Write Access bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.$20$40io_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register$1F$3Fio_flag.bmpYEEPM1RW0EEPM0RWEEP_MODE0EERIEEEProm Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).RW0EEMWEEEMPEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.RW0EEWEEEPEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.RW0EEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.RW0[PIFR:PIM:PMIC2:PMIC1:PMIC0:PCTL:POC:PCNF:PSYNC:POCR_RBH:POCR_RBL:POCR2SBH:POCR2SBL:POCR2RAH:POCR2RAL:POCR2SAH:POCR2SAL:POCR1SBH:POCR1SBL:POCR1RAH:POCR1RAL:POCR1SAH:POCR1SAL:POCR0SBH:POCR0SBL:POCR0RAH:POCR0RAL:POCR0SAH:POCR0SAL]
[POCR_RBH:POCR_RBL];[POCR2SBH:POCR2SBL];[POCR2RAH:POCR2RAL];[POCR2SAH:POCR2SAL];[POCR1SBH:POCR1SBL];[POCR1RAH:POCR1RAL];[POCR1SAH:POCR1SAL];[POCR0SBH:POCR0SBL];[POCR0RAH:POCR0RAL];[POCR0SAH:POCR0SAL]
io_com.bmpPower Stage ControllerPIFRPSC Interrupt Flag RegisterNA$BCregister.bmpYPEV2PSC External Event 2 InterruptRW0PEV1PSC External Event 1 InterruptRW0PEV0PSC External Event 0 InterruptRW0PEOPPSC End of Cycle InterruptRW0PIMPSC Interrupt Mask RegisterNA$BBregister.bmpYPEVE2External Event 2 Interrupt EnableRW0PEVE1External Event 1 Interrupt EnableRW0PEVE0External Event 0 Interrupt EnableRW0PEOPEPSC End of Cycle Interrupt EnableRW0PMIC2PSC Module 2 Input Control RegisterNA$BAregister.bmpYPOVEN2PSC Module 2 Overlap EnableRW0PISEL2PSC Module 2 Input SelectRW0PELEV2PSC Module 2 Input Level SelectorRW0PFLTE2PSC Module 2 Input Filter EnableRW0PAOC2PSC Module 2 Asynchronous Output ControlRW0PRFM22PSC Module 2 Input Mode bit 2RW0PRFM21PSC Module 2 Input Mode bit 1RW0PRFM20PSC Module 2 Input Mode bit 0RW0PMIC1PSC Module 1 Input Control RegisterNA$B9register.bmpYPOVEN1PSC Module 1 Overlap EnableRW0PISEL1PSC Module 1 Input SelectRW0PELEV1PSC Module 1 Input Level SelectorRW0PFLTE1PSC Module 1 Input Filter EnableRW0PAOC1PSC Module 1 Asynchronous Output ControlRW0PRFM12PSC Module 1 Input Mode bit 2RW0PRFM11PSC Module 1 Input Mode bit 1RW0PRFM10PSC Module 1 Input Mode bit 0RW0PMIC0PSC Module 0 Input Control RegisterNA$B8register.bmpYPOVEN0PSC Module 0 Overlap EnableRW0PISEL0PSC Module 0 Input SelectRW0PELEV0PSC Module 0 Input Level SelectorRW0PFLTE0PSC Module 0 Input Filter EnableRW0PAOC0PSC Module 0 Asynchronous Output ControlRW0PRFM02PSC Module 0 Input Mode bit 2RW0PRFM01PSC Module 0 Input Mode bit 1RW0PRFM00PSC Module 0 Input Mode bit 0RW0PCTLPSC Control RegisterNA$B7register.bmpYPPRE1PSC Prescaler Select bit 1RW0PPRE0PSC Prescaler Select bit 0RW0PCLKSELPSC Input Clock SelectRW0PCCYCPSC Complete CycleRW0PRUNPSC RunRW0POCPSC Output ConfigurationNA$B6register.bmpYPOEN2BPSC Output 2B EnableRW0POEN2APSC Output 2A EnableRW0POEN1BPSC Output 1B EnableRW0POEN1APSC Output 1A EnableRW0POEN0BPSC Output 0B EnableRW0POEN0APSC Output 0A EnableRW0PCNFPSC Configuration RegisterNA$B5register.bmpYPULOCKPSC Update LockRW0PMODEPSC ModeRW0POPBPSC Output B PolarityRW0POPAPSC Output A PolarityRW0PSYNCPSC Synchro ConfigurationNA$B4register.bmpYPSYNC21Selection of Synchronization Out for ADCRW0PSYNC20Selection of Synchronization Out for ADCRW0PSYNC11Selection of Synchronization Out for ADCRW0PSYNC10Selection of Synchronization Out for ADCRW0PSYNC01Selection of Synchronization Out for ADCRW0PSYNC00Selection of Synchronization Out for ADCRW0POCR_RBHPSC Output Compare RB Register HighNA$B3register.bmpNPOCR_RB_11RW0POCR_RB_10RW0POCR_RB_9RW0POCR_RB_8RW0POCR_RBLPSC Output Compare RB Register LowNA$B2register.bmpNPOCR_RB_7RW0POCR_RB_6RW0POCR_RB_5RW0POCR_RB_4RW0POCR_RB_3RW0POCR_RB_2RW0POCR_RB_1RW0POCR_RB_0RW0POCR2SBHPSC Module 2 Output Compare SB Register HighNA$B1register.bmpNPOCR2SB_11RW0POCR2SB_10RW0POCR2SB_9RW0POCR2SB_8RW0POCR2SBLPSC Module 2 Output Compare SB Register LowNA$B0register.bmpNPOCR2SB_7RW0POCR2SB_6RW0POCR2SB_5RW0POCR2SB_4RW0POCR2SB_3RW0POCR2SB_2RW0POCR2SB_1RW0POCR2SB_0RW0POCR2RAHPSC Module 2 Output Compare RA Register HighNA$AFregister.bmpNPOCR2RA_11RW0POCR2RA_10RW0POCR2RA_9RW0POCR2RA_8RW0POCR2RALPSC Module 2 Output Compare RA Register LowNA$AEregister.bmpNPOCR2RA_7RW0POCR2RA_6RW0POCR2RA_5RW0POCR2RA_4RW0POCR2RA_3RW0POCR2RA_2RW0POCR2RA_1RW0POCR2RA_0RW0POCR2SAHPSC Module 2 Output Compare SA Register HighNA$ADregister.bmpNPOCR2SA_11RW0POCR2SA_10RW0POCR2SA_9RW0POCR2SA_8RW0POCR2SALPSC Module 2 Output Compare SA Register LowNA$ACregister.bmpNPOCR2SA_7RW0POCR2SA_6RW0POCR2SA_5RW0POCR2SA_4RW0POCR2SA_3RW0POCR2SA_2RW0POCR2SA_1RW0POCR2SA_0RW0POCR1SBHPSC Module 1 Output Compare SB Register HighNA$ABregister.bmpNPOCR1SB_11RW0POCR1SB_10RW0POCR1SB_9RW0POCR1SB_8RW0POCR1SBLPSC Module 1 Output Compare SB Register LowNA$AAregister.bmpNPOCR1SB_7RW0POCR1SB_6RW0POCR1SB_5RW0POCR1SB_4RW0POCR1SB_3RW0POCR1SB_2RW0POCR1SB_1RW0POCR1SB_0RW0POCR1RAHPSC Module 1 Output Compare RA Register HighNA$A9register.bmpNPOCR1RA_11RW0POCR1RA_10RW0POCR1RA_9RW0POCR1RA_8RW0POCR1RALPSC Module 1 Output Compare RA Register LowNA$A8register.bmpNPOCR1RA_7RW0POCR1RA_6RW0POCR1RA_5RW0POCR1RA_4RW0POCR1RA_3RW0POCR1RA_2RW0POCR1RA_1RW0POCR1RA_0RW0POCR1SAHPSC Output Compare SA Register HighNA$A7register.bmpNPOCR1SA_11RW0POCR1SA_10RW0POCR1SA_9RW0POCR1SA_8RW0POCR1SALPSC Module 1 Output Compare SA Register LowNA$A6register.bmpNPOCR1SA_7RW0POCR1SA_6RW0POCR1SA_5RW0POCR1SA_4RW0POCR1SA_3RW0POCR1SA_2RW0POCR1SA_1RW0POCR1SA_0RW0POCR0SBHPSC Output Compare SB Register HighNA$A5register.bmpNPOCR0SB_11RW0POCR0SB_10RW0POCR0SB_9RW0POCR0SB_8RW0POCR0SBLPSC Module 0 Output Compare SB Register LowNA$A4register.bmpNPOCR0SB_7RW0POCR0SB_6RW0POCR0SB_5RW0POCR0SB_4RW0POCR0SB_3RW0POCR0SB_2RW0POCR0SB_1RW0POCR0SB_0RW0POCR0RAHPSC Module 0 Output Compare RA Register HighNA$A3register.bmpNPOCR0RA_11RW0POCR0RA_10RW0POCR0RA_9RW0POCR0RA_8RW0POCR0RALPSC Module 0 Output Compare RA Register LowNA$A2register.bmpNPOCR0RA_7RW0POCR0RA_6RW0POCR0RA_5RW0POCR0RA_4RW0POCR0RA_3RW0POCR0RA_2RW0POCR0RA_1RW0POCR0RA_0RW0POCR0SAHPSC Module 0 Output Compare SA Register HighNA$A1register.bmpNPOCR0SA_11RW0POCR0SA_10RW0POCR0SA_9RW0POCR0SA_8RW0POCR0SALPSC Module 0 Output Compare SA Register LowNA$A0register.bmpNPOCR0SA_7RW0POCR0SA_6RW0POCR0SA_5RW0POCR0SA_4RW0POCR0SA_3RW0POCR0SA_2RW0POCR0SA_1RW0POCR0SA_0RW0[STK500_2:STK500:AVRISPmkII:AVRDragon:STK600:SIMULATOR:JTAGICEmkII:AVRONE]2001002532030x53114510x41256100x400x4C0x000x000x000x418100xC10xC20x000x000x0025625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511510151501050x0F25625650x0525625605050x661110xFF0xFF0xFF012001002532030x53114510x4125660x400x4C0x000x000x000x41450xC10xC20x000x000x0025625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511510151501050x0F25625650x052562560505AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x3a019AVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOExtInterrupt.SimIOExtInterrupt0x0e0x1D0x010x1C0x010x090x400x490x03AVRSimIOExtInterrupt.SimIOExtInterrupt0x100x1D0x020x1C0x020x030x040x490x0cAVRSimIOExtInterrupt.SimIOExtInterrupt0x120x1D0x040x1C0x040x030x200x490x30AVRSimIOExtInterrupt.SimIOExtInterrupt0x140x1D0x080x1C0x080x060x010x490xc0AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x2c0x480x010x1b0x010x4a0x030xffAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x2e0x480x020x1b0x020x4b0x060xffAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x300x480x040x1b0x040x4c0x090xffAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x320x480x080x1b0x080x4d0x030x07AvrSimIOtim8pwmsync2.tim8pwmsync20x001c0x001e0x0020PORTD3PORTE1PINC2AVRSimIOTimert16pwm1.SimIOTimert16pwm10x160x180x1a0x1c0x090x400x090x100x0b0x040x080x02AVRSimIOSPM.SimIOSPM0x3cAVRSimIOSpi.SimIOSpi0x340x030x800x030x010x030x020x090x040x01AvrMasterTimer.MasterTimer12810x382048:4096:8192:16384:32768:65536:131072:262144:524288:1048576AVRSimADC.SimADC0x360xFF0xff0xFF0xFF0x9684DebugWire0xF8,0x7F,0x60,0xF6,0xFF,0x33,0xB9,0xE00xB0,0x6D,0x00,0xE6,0xFF,0x13,0xB8,0xE00X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000x53,0xC2,0xE0,0xDF,0xF7,0x0F,0xF7,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x07,0x5F,0x1D,0xF0,0xFF0x10,0xC2,0xE0,0xD8,0xF7,0x0F,0xF7,0x00,0x00,0x00,0x00,0x00,0x00,0xF7,0x07,0x4D,0x1C,0xF0,0xFF0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x000x570x01000x00080x7E000x00FA0x0000,320x0020,640x000x400x000xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF0xB6,0x01,0x110x310x00000x000x000x7E000x000x3F10010x9684DebugWire