[PACKAGE:POWER:LOCKBIT:PROGRAMMING:FUSE:ADMIN:MEMORY:INTERRUPT_VECTOR:CORE:IO_MODULE:ICE_SETTINGS][TSOP;LGA]28[PV2][PV1][NV][GND][VFET][CF1P][CF1N][CF2P][CF2N][VREG][VREF][VREFGND][PI][NI][PA0][PA1][PA2][PB0][PB1][PB2][PB3][GND][VCC][PC0][BATT][GND][NC][OC]4MHz70CTBD mATBD mATBD uA[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled6110x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabled0x0C0x0CApplication Protection Mode 1: No lock on SPM and LPM in Application Section0x0C0x08Application Protection Mode 2: SPM prohibited in Application Section0x0C0x00Application Protection Mode 3: LPM and SPM prohibited in Application Section0x0C0x04Application Protection Mode 4: LPM prohibited in Application Section0x300x30Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section0x300x20Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section0x300x00Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section0x300x10Boot Loader Protection Mode 4: LPM prohibited in Boot Loader SectionLB1Lock bitLB2Lock bitBLB01Boot Lock bitBLB02Boot Lock bitBLB11Boot lock bitBLB12Boot lock bit0xff,0xdf0xff,0xdf0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x08,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x08,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!0x00,8.0 MHz1284[LOW:HIGH]8WDTONWatchdog Timer Always On1EESAVEEEPROM memory is preserved through chip erase1SPIENEnable Serial programming and Data Downloading0BODENEnable BOD1CKDIV8Divide clock by 80SUT1Select start-up time1SUT0Select start-up time1OSCSEL0Oscillator Select0130x800x00Watch-dog Timer always on; [WDTON=0]0x400x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x200x00Serial program downloading (SPI) enabled; [SPIEN=0]0x01C0x00Start-up time 14 CK + 4 ms; [SUT=000]0x01C0x01Start-up time 14 CK + 8 ms; [SUT=001]0x01C0x02Start-up time 14 CK + 16 ms; [SUT=010]0x01C0x03Start-up time 14 CK + 32 ms; [SUT=011]0x01C0x04Start-up time 14 CK + 64 ms; [SUT=100]0x01C0x05Start-up time 14 CK + 128 ms; [SUT=101]0x01C0x06Start-up time 14 CK + 256 ms; [SUT=110]0x1C0x07Start-up time 14 CK + 512 ms; [SUT=111]; default value4DWENEnable debugWire1BOOTSZ1Select Boot Size0BOOTSZ0Select Boot Size0BOOTRSTSelect Reset Vector170x100x00DUVR mode on; [DUVR=0]0x080x00Debug Wire enable; [DWEN=0]0x060x06Boot Flash section size=512 words Boot start address=$7e00; [BOOTSZ=11]0x060x04Boot Flash section size=1024 words Boot start address=$7c00; [BOOTSZ=10]0x060x02Boot Flash section size=2048 words Boot start address=$3800; [BOOTSZ=01]0x060x00Boot Flash section size=4096 words Boot start address=$7000; [BOOTSZ=00] ; default value0x010x00Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]ATmega64HVE15MHZ1RELEASED$1E$96$1010x31000x006553610244096$100NANA$00$3F$60$FF$20$FFNA0xf60x010x020x040x080x100x200x400x80NA0xf50x010x020x040x080x100x200x400x80NA0xf40x010x020x040x080x100x200x400x80NA0xf30x010x020x040x080x100x200x400x80NA0xf20x010x020x040x080x100x200x400x80NA0xf10x010x020x040x080x100x200x400x80NA0xf00x010x020x040x080x100x200x400x80NA0xef0x010x020x040x080x100x200x400x80NA0xee0x010x020x040x080x100x200x400x80NA0xed0x010x020x040x080x100x200x400x80NA0xec0x010x020x040x080x100x200x400x80NA0xeb0x010x020x040x080x100x200x400x80NA0xea0x010x020x040x080x100x200x400x80NA0xe90x010x020x040x080x100x200x400x80NA0xe80x010x020x040x100x20NA0xe70x010x020x040x100x20NA0xe60x010x020x040x080x100x200x80NA0xe50x010x020x040x080x100x20NA0xe40x010x020x040x080x100x200x80NA0xe30x010x020x040x080x10NA0xe20x010x020x040x08NA0xe10x010x020x040x100x200x40NA0xe00x010x020x04NA0xdc0x010x080x80NA0xd80x010x020x100x20NA0xd40x010x02NA0xd30x010x020x040x080x100x200x400x80NA0xd20x010x020x040x080x100x200x400x80NA0xd10x010x020x04NA0xcA0x010x020x040x080x100x200x400x80NA0xc90x010x020x040x08NA0xc80x010x020x040x080x100x200x400x80NA0xc70x010x020x040x080x100x200x400x80NA0xc60x010x020x040x08NA0xc50x010x020x040x080x100x200x400x80NA0xc40x010x020x040x080x100x200x80NA0xc30x010x020x040x080x100x200x400x80NA0xc20x010x020x040x08NA0xc10x010x020x040x080x100x200x400x80NA0xc00x010x020x040x080x100x200x400x80NA0x890x010x020x040x080x100x200x400x80NA0x880x010x020x040x080x100x200x400x80NA0x850x010x020x040x080x100x200x400x80NA0x840x010x020x040x080x100x200x400x80NA0x82NA0x810x010x020x04NA0x800x010x080x100x200x400x80NA0x7E0x010x02NA0x6F0x010x020x040x08NA0x6E0x010x020x040x08NA0x6C0x010x020x040x080x100x200x400x80NA0x6B0x010x02NA0x690x010x02NA0x680x010x02NA0x670x010x020x040x080x100x200x400x80NA0x660x010x020x040x080x100x200x400x80NA0x640x010x020x040x08NA0x630x010x020x04NA0x620x010x020x040x080x100x400x80NA0x610x010x020x80NA0x600x010x020x040x080x100x200x400x800x3F0x5F0x010x020x040x080x100x200x400x800x3E0x5E0x100x010x020x040x080x100x200x400x800x3D0x5D0xff0x010x020x040x080x100x200x400x800x370x570x010x020x040x080x100x200x400x800x350x550x010x020x100x200x340x540x010x020x040x080x100x330x530x010x020x040x080x310x510x2f0x4f0x2e0x4e0x010x020x040x080x100x200x400x800x2d0x4d0x010x400x800x2c0x4c0x010x020x040x080x100x200x400x800x2B0x4B0x010x020x040x080x100x200x400x800x2A0x4A0x010x020x040x080x100x200x400x800x290x490x010x020x040x080x100x200x400x800x280x480x010x020x040x080x100x200x400x800x270x470x010x020x040x080x100x200x400x800x260x460x010x020x040x080x100x200x400x800x250x450x010x020x040x240x440x010x080x100x200x400x800x230x430x010x800x220x420x010x020x210x410x010x020x040x080x100x200x400x800x200x400x010x020x040x080x100x200x400x800x1F0x3F0x010x020x040x080x100x200x1E0x3E0x010x020x040x080x100x200x400x800x1D0x3D0x010x1C0x3C0x010x1B0x3B0x010x020x160x360x010x020x040x080x150x350x010x020x040x080x050x250x010x020x040x080x100x200x400x800x040x240x010x020x040x080x100x200x400x800x030x230x010x020x040x080x100x200x400x800x020x220x010x020x010x210x010x020x000x200x010x02$7000$7FFF$0000$6FFF645128$0000$7e00$7e00102416$0000$7c00$7c00204832$0000$7800$7800409664$0000$7000$700025$0000RESETExternal Pin, Power-on Reset, Brown-out Reset and Watchdog Reset$0002INT0External Interrupt 0$0004PCINT0Pin Change Interrupt 0$0006PCINT1Pin Change Interrupt 1$0008WDTWatchdog Timeout Interrupt$000aWAKEUPWakeup Timer Overflow$000cTIMER1_ICTimer 1 Input capture$000eTIMER1_COMPATimer 1 Compare Match A$0010TIMER1_COMPBTimer 1 Compare Match B$0012TIMER1_OVFTimer 1 overflow$0014TIMER0_ICTimer 0 Input Capture$0016TIMER0_COMPATimer 0 Comapre Match A$0018TIMER0_COMPBTimer 0 Compare Match B$001aTIMER0_OVFTimer 0 Overflow$001cLIN STATUSLIN Status Interrupt$001eLIN_ERRORLIN Error Interrupt$0020SPI_STCSPI Serial transfer complete$0022VADC_CONVVoltage ADC Instantaneous Conversion Complete$0024VADC_ACCVoltage ADC Accumulated Conversion Complete$0026CADC_CONVC-ADC Instantaneous Conversion Complete$0028CADC_REG_CURC-ADC Regular Current$002aCADC_ACCC-ADC Accumulated Conversion Complete$02cEE_READYEEPROM Ready$02eSPMSPM Ready$030PLLPLL Lock Change InterruptV2EAVRSimCoreV2.SimCoreV2[][][]32$00$1B$1A$1D$1C$1F$1EMEXT32/64-bit Math Extension1[SPI:EEPROM:TIMER_COUNTER_1:PORTB:TIMER_COUNTER_0:BOOT_LOAD:AD_CONVERTER:PORTA:BANDGAP:LINUART:CPU:EXTERNAL_INTERRUPT:WATCHDOG:WAKEUP_TIMER][SPDR:SPSR:SPCR]io_com.bmpThe Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)SPCRSPI Control Register0x2c0x4cio_flag.bmpYSPIESPI Interrupt EnableThis bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.RW0SPESPI EnableWhen the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.RW0DORDData OrderWhen the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.RW0MSTRMaster/Slave SelectThis bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.RW0CPOLClock polarityWhen this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.RW0CPHAClock PhaseRefer to Figure 36 or Figure 37 for the functionality of this bit.RW0SPR1SPI Clock Rate Select 1These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RW0SPR0SPI Clock Rate Select 0These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RWCOMM_SCK_RATE_3BIT0SPSRSPI Status Register0x2d0x4dio_flag.bmpYSPIFSPI Interrupt FlagWhen a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).R0WCOLWrite Collision FlagThe WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.R0SPI2XDouble SPI Speed BitWhen this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading. RW0SPDRSPI Data RegisterThe SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.0x2e0x4eio_com.bmpNSPDR7SPI Data Register bit 7RWXSPDR6SPI Data Register bit 6RWXSPDR5SPI Data Register bit 5RWXSPDR4SPI Data Register bit 4RWXSPDR3SPI Data Register bit 3RWXSPDR2SPI Data Register bit 2RWXSPDR1SPI Data Register bit 1R0SPDR0SPI Data Register bit 0R0[EEARH:EEARL:EEDR:EECR]
[EEARH:EEARL]
io_cpu.bmpEEPROM_m32HVB.xmlEEARHEEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction0x220x42io_cpu.bmpNEEAR9EEPROM Read/Write Access bit 9RW0EEAR8EEPROM Read/Write Access bit 8RW0EEARLEEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction0x210x41io_cpu.bmpNEEAR7EEPROM Read/Write Access bit 7RW0EEAR6EEPROM Read/Write Access bit 6RW0EEAR5EEPROM Read/Write Access bit 5RW0EEAR4EEPROM Read/Write Access bit 4RW0EEAR3EEPROM Read/Write Access bit 3RW0EEAR2EEPROM Read/Write Access bit 2RW0EEAR1EEPROM Read/Write Access bit 1RW0EEAR0EEPROM Read/Write Access bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.0x200x40io_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register0x1F0x3Fio_flag.bmpYEEPM1RW0EEPM0RWEEP_MODE0EERIEEEProm Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).RW0EEMPEEEMWEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.RW0EEPEEEWEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.RW0EEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.RW0[TCCR1A:TCCR1B:TCNT1H:TCNT1L:OCR1A:OCR1B:TIMSK1:TIFR1:GTCCR]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL]
io_timer.bmpTCCR1BTimer/Counter1 Control Register BNA0x81io_flag.bmpYCS12Clock Select1 bit 2RW0CS11Clock Select1 bit 1RW0CS10Clock Select1 bit 0RWCLK_SEL_3BIT_EXT0TCCR1ATimer/Counter 1 Control Register ANA0x80io_flag.bmpYTCW1Timer/Counter WidthWhen this bit is written to one 16-bit mode is selected. RW0ICEN1Input Capture Mode EnableThe Input Capture Mode is enabled when this bit is written to one.RW0ICNC1Input Capture Noise CancelerSetting this bit activates the Input Capture Noise Canceler. RW0ICES1Input Capture Edge SelectThis bit selects which edge on the Input Capture Source that is used to trigger a capture event.RW0ICS1Input Capture SelectWhen written logic one, this bit enables the input capture function in Timer/Counter to be triggered by the alternative Input Capture Source.RW0WGM10Waveform Generation ModeThis bit controls the counting sequence of the counterRW0TCNT1HTimer Counter 1 High ByteNA0x85io_timer.bmpNTCNT1H7Timer Counter 1 High Byte bit 7RW0TCNT1H6Timer Counter 1 High Byte bit 6RW0TCNT1H5Timer Counter 1 High Byte bit 5RW0TCNT1H4Timer Counter 1 High Byte bit 4RW0TCNT1H3Timer Counter 1 High Byte bit 3RW0TCNT1H2Timer Counter 1 High Byte bit 2RW0TCNT1H1Timer Counter 1 High Byte bit 1RW0TCNT1H0Timer Counter 1 High Byte bit 0RW0TCNT1LTimer Counter 1 Low ByteNA0x84io_timer.bmpNTCNT1L7Timer Counter 1 Low Byte bit 7RW0TCNT1L6Timer Counter 1 Low Byte bit 6RW0TCNT1L5Timer Counter 1 Low Byte bit 5RW0TCNT1L4Timer Counter 1 Low Byte bit 4RW0TCNT1L3Timer Counter 1 Low Byte bit 3RW0TCNT1L2Timer Counter 1 Low Byte bit 2RW0TCNT1L1Timer Counter 1 Low Byte bit 1RW0TCNT1L0Timer Counter 1 Low Byte bit 0RW0OCR1AOutput Compare Register 1A The Output Compare Register A contains an 8-bit value that is continuously compared with theNA0x88io_timer.bmpNOCR1A7RW0OCR1A6RW0OCR1A5RW0OCR1A4RW0OCR1A3RW0OCR1A2RW0OCR1A1RW0OCR1A0RW0OCR1BOutput Compare Register B NA0x89io_timer.bmpNOCR1B7RW0OCR1B6RW0OCR1B5RW0OCR1B4RW0OCR1B3RW0OCR1B2RW0OCR1B1RW0OCR1B0RW0TIMSK1Timer/Counter Interrupt Mask RegisterNA0x6Fio_flag.bmpYICIE1Timer/Counter n Input Capture Interrupt EnableRW0OCIE1BTimer/Counter1 Output Compare B Interrupt EnableRW0OCIE1ATimer/Counter1 Output Compare A Interrupt EnableRW0TOIE1Timer/Counter1 Overflow Interrupt EnableRW0TIFR1Timer/Counter Interrupt Flag register0x160x36io_flag.bmpYICF1Timer/Counter 1 Input Capture FlagRW0OCF1BTimer/Counter1 Output Compare Flag BRW0OCF1ATimer/Counter1 Output Compare Flag ARW0TOV1Timer/Counter1 Overflow FlagRW0GTCCRGeneral Timer/Counter Control Register0x230x43io_flag.bmpYTSMTimer/Counter Synchronization ModeRW0PSRSYNCPrescaler ResetRW0[PORTB:DDRB:PINB:PBOV]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register0x050x25io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register0x040x24io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.0x030x23io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0PBOVPort B OverrideNA0xdcio_flag.bmpYPBOVCEPort B Override Change EnableRW0PBOE3Port B Override Enable 3RW0PBOE0Port B Override Enable 0RW0[TCCR0A:TCCR0B:TCNT0H:TCNT0L:OCR0A:OCR0B:TIMSK0:TIFR0:GTCCR]
[TCNT0H:TCNT0L];[OCR0AH:OCR0AL]
io_timer.bmpTCCR0BTimer/Counter0 Control Register B0x250x45io_flag.bmpYCS02Clock Select0 bit 2RW0CS01Clock Select0 bit 1RW0CS00Clock Select0 bit 0RWCLK_SEL_3BIT_EXT0TCCR0ATimer/Counter 0 Control Register A0x240x44io_flag.bmpYTCW0Timer/Counter WidthWhen this bit is written to one 16-bit mode is selected. RW0ICEN0Input Capture Mode EnableThe Input Capture Mode is enabled when this bit is written to one.RW0ICNC0Input Capture Noise CancelerSetting this bit activates the Input Capture Noise Canceler. RW0ICES0Input Capture Edge SelectThis bit selects which edge on the Input Capture Source that is used to trigger a capture event.RW0ICS0Input Capture SelectWhen written logic one, this bit enables the input capture function in Timer/Counter to be triggered by the alternative Input Capture Source.RW0WGM00Waveform Generation ModeThis bit controls the counting sequence of the counterRW0TCNT0HTimer Counter 0 High Byte0x270x47io_timer.bmpNTCNT0H7Timer Counter 0 High Byte bit 7RW0TCNT0H6Timer Counter 0 High Byte bit 6RW0TCNT0H5Timer Counter 0 High Byte bit 5RW0TCNT0H4Timer Counter 0 High Byte bit 4RW0TCNT0H3Timer Counter 0 High Byte bit 3RW0TCNT0H2Timer Counter 0 High Byte bit 2RW0TCNT0H1Timer Counter 0 High Byte bit 1RW0TCNT0H0Timer Counter 0 High Byte bit 0RW0TCNT0LTimer Counter 0 Low Byte0x260x46io_timer.bmpNTCNT0L7Timer Counter 0 Low Byte bit 7RW0TCNT0L6Timer Counter 0 Low Byte bit 6RW0TCNT0L5Timer Counter 0 Low Byte bit 5RW0TCNT0L4Timer Counter 0 Low Byte bit 4RW0TCNT0L3Timer Counter 0 Low Byte bit 3RW0TCNT0L2Timer Counter 0 Low Byte bit 2RW0TCNT0L1Timer Counter 0 Low Byte bit 1RW0TCNT0L0Timer Counter 0 Low Byte bit 0RW0OCR0AOutput Compare Register 0A The Output Compare Register A contains an 8-bit value that is continuously compared with the0x280x48io_timer.bmpNOCR0A7RW0OCR0A6RW0OCR0A5RW0OCR0A4RW0OCR0A3RW0OCR0A2RW0OCR0A1RW0OCR0A0RW0OCR0BOutput Compare Register B 0x290x49io_timer.bmpNOCR0B7RW0OCR0B6RW0OCR0B5RW0OCR0B4RW0OCR0B3RW0OCR0B2RW0OCR0B1RW0OCR0B0RW0TIMSK0Timer/Counter Interrupt Mask RegisterNA0x6Eio_flag.bmpYICIE0Timer/Counter n Input Capture Interrupt EnableRW0OCIE0BTimer/Counter0 Output Compare B Interrupt EnableRW0OCIE0ATimer/Counter0 Output Compare A Interrupt EnableRW0TOIE0Timer/Counter0 Overflow Interrupt EnableRW0TIFR0Timer/Counter Interrupt Flag register0x150x35io_flag.bmpYICF0Timer/Counter 0 Input Capture FlagRW0OCF0BTimer/Counter0 Output Compare Flag BRW0OCF0ATimer/Counter0 Output Compare Flag ARW0TOV0Timer/Counter0 Overflow FlagRW0GTCCRGeneral Timer/Counter Control Register0x230x43io_flag.bmpYTSMTimer/Counter Synchronization ModeRW0PSRSYNCPrescaler ResetRW0[SPMCSR]io_cpu.bmpAVRSimIOSPM.SimIOSPMThe Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write supporSPMCSRStore Program Memory Control and Status RegisterThe Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.0x370x57io_flag.bmpYSPMIESPM Interrupt EnableRW0RWWSBRead-While-Write Section BusyR0SIGRDSignature Row ReadRW0RWWSRERead-While-Write Section Read EnableRW0LBSETLock Bit SetRW0PGWRTPage WriteRW0PGERSPage EraseRW0SPMENStore Program Memory EnableRW0[ADSCSRA:ADSCSRB:ADCRA:ADCRB:ADCRC:ADCRD:ADCRE:ADIFR:ADIMR:CADRCLH:CADRCLL:VADICH:VADICL:VADAC3:VADAC2:VADAC1:VADAC0:CADICH:CADICL:CADAC3:CADAC2:CADAC1:CADAC0]
[CADCRLH:CADCRLL];[VADICH:VADICL];[VADAC3:VADAC2:VADAC1:VADAC0];[CADICH:CADICL];[CADAC3:CADAC2:CADAC1:CADAC0]
io_analo.bmpSynchronous Current and Voltage ADCADSCSRAADC Synchronization Control and Status RegisterNA0xe0io_analo.bmpYSBSYSynchronization BusySynchronization BusyR0SCMD1Synchronization CommandSynchronization CommandRW0SCMD0Synchronization CommandSynchronization CommandRWSYNCHRONIZATION_COMMAND0ADSCSRBADC Synchronization Control and Status RegisterNA0xe1io_analo.bmpYVADICPSV-ADC Instantaneous Conversion Polarity StatusV-ADC Instantaneous Conversion Polarity StatusR0VADACRBVADAC Data Read Out BusyVADAC Data Read Out BusyR0VADICRBVADIC Data Read Out BusyVADIC Data Data Read Out BusyR0CADICPSC-ADC Instantaneous Conversion Polarity StatusC-ADC Instantaneous Conversion Polarity StatusR0CADACRBCADAC Data Read Out BusyCADAC Data Read Out BusyR0CADICRBCADIC Data Read Out BusyCADIC Data Read Out BusyR0ADCRAADC Control Register ANA0xe2io_analo.bmpYADPSELADC Polarity SelectRW0ADCMS1C-ADC Chopper Mode SelectRW0ADCMS0C-ADC Chopper Mode SelectRWC_ADC_CHOPPER_MODE_SELECT0CKSELSampling Clock SelectRWSAMPLING CLOCK SELECT0ADCRBADC Control Register BNA0xe3io_analo.bmpYADIDES1Instantaneous Decimation Ratio SelectRW0ADIDES0Instantaneous Decimation Ratio SelectRWINSTANTANEOUS_DECIMATION_RATIO_SELECT0ADADES2Accumulated Decimation Ratio SelectRW0ADADES1Accumulated Decimation Ratio SelectRW0ADADES0Accumulated Decimation Ratio SelectRWACCUMULATED_DECIMATION_RATIO_SELECT0ADCRCADC Control Register BNA0xe4io_analo.bmpYCADENC-ADC EnableRW0CADRCM1C-ADC Regular Current Comparator ModeRW0CADRCM0C-ADC Regular Current Comparator ModeRWC_ADC_REGULAR_CURRENT_COMPARATOR_MODE0CADRCT3C-ADC Regular Current Count ThresholdRW0CADRCT2C-ADC Regular Current Count ThresholdRW0CADRCT1C-ADC Regular Current Count ThresholdRW0CADRCT0C-ADC Regular Current Count ThresholdRWMISC_4BIT_COUNT0ADCRDADC Control Register DNA0xe5io_analo.bmpYCADG2C-ADC GainRW0CADG1C-ADC GainRW0CADG0C-ADC GainRWC_ADC_INPUT_GAIN0CADPDM1C-ADC Pin Diagnostics ModeRW0CADPDM0C-ADC Pin Diagnostics ModeRWC_ADC_PIN_DIAGNOSIS_MODE0CADDSELC-ADC Diagnostics Channel SelectRW0ADCREADC Control Register ENA0xe6io_analo.bmpYVADENV-ADC EnableRW0VADREFSV-ADC Reference SelectRWV_ADC_REFERENCE_SELECT0VADPDM1V-ADC Pin Diagnostics ModeRW0VADPDM0V-ADC Pin Diagnostics ModeRWV_ADC_PIN_DIAGNOSIS_MODE0VADMUX2V-ADC Channel SelectRW0VADMUX1V-ADC Channel SelectRW0VADMUX0V-ADC Channel SelectRWV_ADC_CHANNEL_SELECT0ADIFRADC Interrupt Flag RegisterNA0xe7io_analo.bmpYVADACIFV-ADC Accumulated Voltage Interrupt FlagRW0VADICIFV-DAC Instantaneous Voltage Interrupt FlagRW0CADRCIFC-ADC Regulator Current Interrupt FlagRW0CADACIFC-ADC Accumulated Current Interrupt FlagRW0CADICIFC-ADC Instantaneous Current Interrupt FlagRW0ADIMRADC Interrupt Mask RegisterNA0xe8io_analo.bmpYVADACIEV-ADC Accumulated Voltage Interrupt EnableRW0VADICIEV-DAC Instantaneous Voltage Interrupt EnableRW0CADRCIEC-ADC Regulator Current Interrupt EnableRW0CADACIEC-ADC Accumulated Current Interrupt EnableRW0CADICIEC-ADC Instantaneous Current Interrupt EnableRW0CADRCLHCC-ADC Regulator Current Comparator Threshold LevelNA0xeaio_analo.bmpNCADRCL15RW0CADRCL14RW0CADRCL13RW0CADRCL12RW0CADRCL11RW0CADRCL10RW0CADRCL9RW0CADRCL8RW0CADRCLLCC-ADC Regulator Current Comparator Threshold LevelNA0xe9io_analo.bmpNCADRCL7RW0CADRCL6RW0CADRCL5RW0CADRCL4RW0CADRCL3RW0CADRCL2RW0CADRCL1RW0CADRCL0RW0VADICHV-ADC Instantaneous Conversion ResultNA0xf2io_analo.bmpNVADIC15R0VADIC14R0VADIC13R0VADIC12R0VADIC11R0VADIC10R0VADIC9R0VADIC8R0VADICLV-ADC Instantaneous Conversion ResultNA0xf1io_analo.bmpNVADIC7R0VADIC6R0VADIC5R0VADIC4R0VADIC3R0VADIC2R0VADIC1R0VADIC0R0VADAC3V-ADC Accumulated Conversion ResultNA0xf6io_analo.bmpNVADAC31R0VADAC30R0VADAC29R0VADAC28R0VADAC27R0VADAC26R0VADAC25R0VADAC24R0VADAC2V-ADC Accumulated Conversion ResultNA0xf5io_analo.bmpNVADAC23R0VADAC22R0VADAC21R0VADAC20R0VADAC19R0VADAC18R0VADAC17R0VADAC16R0VADAC1V-ADC Accumulated Conversion ResultNA0xf4io_analo.bmpNVADAC15R0VADAC14R0VADAC13R0VADAC12R0VADAC11R0VADAC10R0VADAC09R0VADAC08R0VADAC0V-ADC Accumulated Conversion ResultNA0xf3io_analo.bmpNVADAC07R0VADAC06R0VADAC05R0VADAC04R0VADAC03R0VADAC02R0VADAC01R0VADAC00R0CADICHC-ADC Instantaneous Conversion ResultNA0xecio_analo.bmpNCADIC15R0CADIC14R0CADIC13R0CADIC12R0CADIC11R0CADIC10R0CADIC9R0CADIC8R0CADICLC-ADC Instantaneous Conversion ResultNA0xebio_analo.bmpNCADIC7R0CADIC6R0CADIC5R0CADIC4R0CADIC3R0CADIC2R0CADIC1R0CADIC0R0CADAC3C-ADC Accumulated Conversion ResultNA0xf0io_analo.bmpNCADAC31R0CADAC30R0CADAC29R0CADAC28R0CADAC27R0CADAC26R0CADAC25R0CADAC24R0CADAC2C-ADC Accumulated Conversion ResultNA0xefio_analo.bmpNCADAC23R0CADAC22R0CADAC21R0CADAC20R0CADAC19R0CADAC18R0CADAC17R0CADAC16R0CADAC1C-ADC Accumulated Conversion ResultNA0xeeio_analo.bmpNCADAC15R0CADAC14R0CADAC13R0CADAC12R0CADAC11R0CADAC10R0CADAC09R0CADAC08R0CADAC0C-ADC Accumulated Conversion ResultNA0xedio_analo.bmpNCADAC07R0CADAC06R0CADAC05R0CADAC04R0CADAC03R0CADAC02R0CADAC01R0CADAC00R0[PORTA:DDRA:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTAPort A Data Register0x020x22io_port.bmpNPORTA1Port A Data Register bit 1RW0PORTA0Port A Data Register bit 0RW0DDRAPort A Data Direction Register0x010x21io_flag.bmpNDDA1Data Direction Register, Port A, bit 1RW0DDA0Data Direction Register, Port A, bit 0RW0PINAPort A Input PinsThe Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.0x000x20io_port.bmpNPINA1Input Pins, Port A bit 1RWHi-ZPINA0Input Pins, Port A bit 0RWHi-Z[BGCSRA:BGCRA:BGCRB:BGLR]io_analo.bmpBGCSRABandgap Control and Status Register ANA0xd1io_analo.bmpYBGSC2Band Gap Sample ConfigurationRW0BGSC1Band Gap Sample ConfigurationRW0BGSC0Band Gap Sample ConfigurationRW0BGCRABand Gap Calibration Register ANA0xd3io_analo.bmpYBGCN7Band Gap Calibration NominalRW0BGCN6Band Gap Calibration NominalRW0BGCN5Band Gap Calibration NominalRW0BGCN4Band Gap Calibration NominalRW0BGCN3Band Gap Calibration NominalRW0BGCN2Band Gap Calibration NominalRW0BGCN1Band Gap Calibration NominalRW0BGCN0Band Gap Calibration NominalRW0BGCRBBand Gap Calibration Register BNA0xd2io_analo.bmpYBGCL7Band Gap Calibration LinearRW0BGCL6Band Gap Calibration LinearRW0BGCL5Band Gap Calibration LinearR0BGCL4Band Gap Calibration LinearRW0BGCL3Band Gap Calibration LinearRW0BGCL2Band Gap Calibration LinearRW0BGCL1Band Gap Calibration LinearRW0BGCL0Band Gap Calibration LinearRW0BGLRBand Gap Lock RegisterNA0xd4io_analo.bmpYBGPLEBand Gap Lock EnableRW0BGPLBand Gap LockRW0[LINCR:LINSIR:LINENIR:LINERR:LINBTR:LINBRRL:LINBRRH:LINDLR:LINIDR:LINSEL:LINDAT]io_com.bmpLIN or UART InterfaceLINCRLIN Control RegisterNA0xc0io_analo.bmpYLSWRESSoftware ResetRW0LIN13LIN StandardRW0LCONF1LIN Configuration bit 1RW0LCONF0LIN Configuration bit 0RW0LENALIN or UART EnableRW0LCMD2LIN Command and Mode bit 2RW0LCMD1LIN Command and Mode bit 1RW0LCMD0LIN Command and Mode bit 0RW0LINSIRLIN Status and Interrupt RegisterNA0xc1io_flag.bmpYLIDST2Identifier Status bit 2R0LIDST1Identifier Status bit 1R0LIDST0Identifier Status bit 0R0LBUSYBusy SignalR0LERRError InterruptRW0LIDOKIdentifier InterruptRW0LTXOKTransmit Performed InterruptRW0LRXOKReceive Performed InterruptRW0LINENIRLIN Enable Interrupt RegisterNA0xc2io_analo.bmpYLENERREnable Error InterruptRW0LENIDOKEnable Identifier InterruptRW0LENTXOKEnable Transmit Performed InterruptRW0LENRXOKEnable Receive Performed InterruptRW0LINERRLIN Error RegisterNA0xc3io_flag.bmpYLABORTAbort FlagR0LTOERRFrame Time Out Error FlagR0LOVERROverrun Error FlagR0LFERRFraming Error FlagR0LSERRSynchronization Error FlagR0LPERRParity Error FlagR0LCERRChecksum Error FlagR0LBERRBit Error FlagR0LINBTRLIN Bit Timing RegisterNA0xc4io_flag.bmpYLDISRDisable Bit Timing ResynchronizationRW0LBT5LIN Bit Timing bit 5RW1LBT4LIN Bit Timing bit 4RW0LBT3LIN Bit Timing bit 3RW0LBT2LIN Bit Timing bit 2RW0LBT1LIN Bit Timing bit 1RW0LBT0LIN Bit Timing bit 0RW0LINBRRLLIN Baud Rate Low RegisterNA0xc5io_timer.bmpYLDIV7RW0LDIV6RW0LDIV5RW0LDIV4RW0LDIV3RW0LDIV2RW0LDIV1RW0LDIV0RW0LINBRRHLIN Baud Rate High RegisterNA0xc6io_timer.bmpYLDIV11RW0LDIV10RW0LDIV9RW0LDIV8RW0LINDLRLIN Data Length RegisterNA0xc7io_com.bmpYLTXDL3LIN Transmit Data Length bit 3RW0LTXDL2LIN Transmit Data Length bit 2RW0LTXDL1LIN Transmit Data Length bit 1RW0LTXDL0LIN Transmit Data Length bit 0RW0LRXDL3LIN Receive Data Length bit 3RW0LRXDL2LIN Receive Data Length bit 2RW0LRXDL1LIN Receive Data Length bit 1RW0LRXDL0LIN Receive Data Length bit 0RW0LINIDRLIN Identifier RegisterNA0xc8io_com.bmpYLP1Parity bit 1R0LP0Parity bit 0R0LID5Identifier bit 5 or Data Length bit 1RW0LID4Identifier bit 4 or Data Length bit 0RW0LID3Identifier bit 3RW0LID2Identifier bit 2RW0LID1Identifier bit 1RW0LID0Identifier bit 0RW0LINSELLIN Data Buffer Selection RegisterNA0xc9io_com.bmpYLAINCAuto Increment of Data Buffer Index (Active Low)RW0LINDX2FIFO LIN Data Buffer Index bit 2RW0LINDX1FIFO LIN Data Buffer Index bit 1RW0LINDX0FIFO LIN Data Buffer Index bit 0RW0LINDATLIN Data RegisterNA0xcAio_com.bmpYLDATA7RW0LDATA6RW0LDATA5RW0LDATA4RW0LDATA3RW0LDATA2RW0LDATA1RW0LDATA0RW0[SREG:SPH:SPL:MCUCR:MCUSR:SOSCCALA:SOSCCALB:PLLCSR:SMCR:GPIOR2:GPIOR1:GPIOR0:DIDR0:PRR0:CLKPR]
[SPH:SPL]
io_cpu.bmpSREGStatus Register0x3F0x5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPHStack Pointer High0x3E0x5Eio_sph.bmpNSP15Stack pointer bit 15RW0SP14Stack pointer bit 14RW0SP13Stack pointer bit 13RW0SP12Stack pointer bit 12RW0SP11Stack pointer bit 11RW0SP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW0SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D0x5Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.0x350x55io_flag.bmpYCKOEClock Output EnableWhen this bit is written to one, the CPU clock divided by 4 is output on the CKOUT pin. The CKOUT pin will be tri-stated when this bit is zero.RW0PUDPull-up disableWhen this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). RW0IVSELInterrupt Vector SelectRW0IVCEInterrupt Vector Change EnableRW0MCUSRMCU Status RegisterThe MCU Status Register provides information on which reset source caused an MCU reset.0x340x54io_flag.bmpYOCDRFOCD Reset FlagRW0WDRFWatchdog Reset FlagThis bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.RW0BODRFBrown-out Reset FlagThis bit is set if a Brown-out Reset occurs. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.RW0EXTRFExternal Reset FlagThis bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.RW0PORFPower-on reset flagThis bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.RW0SOSCCALASlow Oscillator Calibration Register AThe Slow RC Oscillator Calibration Register A is used to trim the Slow RC Oscillator. The factory-calibrated value is automatically written to this register during chip reset, and should not be changed by the SW. The Slow RC Oscillator Calibration Register A is protected by a timed sequence.NA0x66io_cpu.bmpNSCALA7Oscillator Calibration Value Bit7RW0SCALA6Oscillator Calibration Value Bit6RW0SCALA5Oscillator Calibration Value Bit5RW0SCALA4Oscillator Calibration Value Bit4RW0SCALA3Oscillator Calibration Value Bit3RW0SCALA2Oscillator Calibration Value Bit2RW0SCALA1Oscillator Calibration Value Bit1RW0SCALA0Oscillator Calibration Value Bit0RW0SOSCCALBOscillator Calibration Register BThe Slow RC Oscillator Calibration Register B is used to trim the Slow RC Oscillator. The factory-calibrated value is automatically written to this register during chip reset, and should not be changed by the SW. The Slow RC Oscillator Calibration Register B is protected by a timed sequence. NA0x67io_cpu.bmpNSCALB7Oscillator Calibration Value Bit7RW0SCALB6Oscillator Calibration Value Bit6RW0SCALB5Oscillator Calibration Value Bit5RW0SCALB4Oscillator Calibration Value Bit4RW0SCALB3Oscillator Calibration Value Bit3RW0SCALB2Oscillator Calibration Value Bit2RW0SCALB1Oscillator Calibration Value Bit1RW0SCALB0Oscillator Calibration Value Bit0RW0PLLCSRPLL Control and Status RegisterNA0xd8io_cpu.bmpYSWENPLL Software EnableR0LOCKPLL LockR0PLLCIFPLL Lock Change Interrupt FlagRW0PLLCIEPLL Lock Change Interrupt EnableRW0SMCRSleep Mode Control RegisterThe Sleep Mode Control Register contains control bits for power management.0x330x53io_cpu.bmpYSM2Sleep Mode Select bit 2These bits select between the five available sleep modes.RW0SM1Sleep Mode Select bit 1These bits select between the five available sleep modes.RW0SM0Sleep Mode Select bit 0These bits select between the five available sleep modes.RW0SESleep EnableThe SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.ToRW0GPIOR2General Purpose IO Register 2This device contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2B0x4Bio_cpu.bmpNGPIOR27General Purpose IO Register 2 bit 7RW0GPIOR26General Purpose IO Register 2 bit 6RW0GPIOR25General Purpose IO Register 2 bit 5RW0GPIOR24General Purpose IO Register 2 bit 4RW0GPIOR23General Purpose IO Register 2 bit 3RW0GPIOR22General Purpose IO Register 2 bit 2RW0GPIOR21General Purpose IO Register 2 bit 1RW0GPIOR20General Purpose IO Register 2 bit 0RW0GPIOR1General Purpose IO Register 1This device contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2A0x4Aio_cpu.bmpNGPIOR17General Purpose IO Register 1 bit 7RW0GPIOR16General Purpose IO Register 1 bit 6RW0GPIOR15General Purpose IO Register 1 bit 5RW0GPIOR14General Purpose IO Register 1 bit 4RW0GPIOR13General Purpose IO Register 1 bit 3RW0GPIOR12General Purpose IO Register 1 bit 2RW0GPIOR11General Purpose IO Register 1 bit 1RW0GPIOR10General Purpose IO Register 1 bit 0RW0GPIOR0General Purpose IO Register 0This device contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x1E0x3Eio_cpu.bmpNGPIOR07General Purpose IO Register 0 bit 7RW0GPIOR06General Purpose IO Register 0 bit 6RW0GPIOR05General Purpose IO Register 0 bit 5RW0GPIOR04General Purpose IO Register 0 bit 4RW0GPIOR03General Purpose IO Register 0 bit 3RW0GPIOR02General Purpose IO Register 0 bit 2RW0GPIOR01General Purpose IO Register 0 bit 1RW0GPIOR00General Purpose IO Register 0 bit 0RW0DIDR0Digital Input Disable RegisterNA0x7Eio_cpu.bmpYPA1DIDWhen this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.RW0PA0DIDWhen this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.RW0PRR0Power Reduction Register 0NA0x64io_cpu.bmpYPRLINPower Reduction LIN UART InterfaceRW0PRSPIPower reduction SPIRW0PRTIM1Power Reduction Timer/Counter1Writing a logic one to this bit shuts down the Timer/Counter1 module. When the, Timer/Counter1 is enabled, operation will continue like before the shutdown.RW0PRTIM0Power Reduction Timer/Counter0Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.RW0CLKPRClock Prescale RegisterNA0x61io_cpu.bmpYCLKPCEClock Prescaler Change EnableRW0CLKPS1Clock Prescaler Select Bit 1RW1CLKPS0Clock Prescaler Select Bit 0RW1[EICRA:EIMSK:EIFR:PCICR:PCIFR:PCMSK1:PCMSK0]io_ext.bmpThe external interrupts are triggered by the INT3:0 pins or any of the PCINT11:0 pins.EICRAExternal Interrupt Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.NA0x69io_flag.bmpYISC01External Interrupt Sense Control 0 Bit 1 RW0ISC00External Interrupt Sense Control 0 Bit 0RWINTERRUPT_SENSE_CONTROL0EIMSKExternal Interrupt Mask Register0x1D0x3Dio_flag.bmpYINT0External Interrupt Request 0 EnableRW0EIFRExternal Interrupt Flag Register0x1C0x3Cio_flag.bmpYINTF0External Interrupt Flag 0RW0PCICRPin Change Interrupt Control RegisterNA0x68io_flag.bmpYPCIE1Pin Change Interrupt Enable 1RW0PCIE0Pin Change Interrupt Enable 0RW0PCIFRPin Change Interrupt Flag Register0x1B0x3Bio_flag.bmpYPCIF1Pin Change Interrupt Flag 1RW0PCIF0Pin Change Interrupt Flag 1RW0PCMSK1Pin Change Enable Mask Register 1NA0x6Cio_flag.bmpNPCINT9Pin Change Enable Mask 9RW0PCINT8Pin Change Enable Mask 8RW0PCINT7Pin Change Enable Mask 7RW0PCINT6Pin Change Enable Mask 6RW0PCINT5Pin Change Enable Mask 5RW0PCINT4Pin Change Enable Mask 4RW0PCINT3Pin Change Enable Mask 3RW0PCINT2Pin Change Enable Mask 2RW0PCMSK0Pin Change Enable Mask Register 0NA0x6Bio_flag.bmpNPCINT1Pin Change Enable Mask 1RW0PCINT0Pin Change Enable Mask 0RW0[WDTCSR:WDTCLR]io_watch.bmpWDTCSRWatchdog Timer Control RegisterNA0x60io_flag.bmpYWDIFWatchdog Timeout Interrupt FlagRW0WDIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2WDOG_TIMER_PRESCALE_4BITSRW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0WDTCLRWatchdog Timer Configuration Lock RegisterNA0x63io_flag.bmpYWDCL1Watchdog Timer Comfiguration Lock bit 1RW0WDCL0Watchdog Timer Comfiguration Lock bit 0RW0WDCLEWatchdog Timer Comfiguration Lock EnableRW0[WUTCSR]io_timer.bmpt8pwm1_01WUTCSRWake-up Timer Control and Status RegisterNA0x62io_flag.bmpYWUTIFWake-up Timer Interrupt FlagThe bit WUTIF is set (one) when an overflow occurs in the Wake-up Timer. WUTIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, WUTIE (Wake-up Timer Interrupt Enable), and WUTIF are set (one), the Wake-up Timer interrupt is executed.RW0WUTIEWake-up Timer Interrupt EnableWhen the WUTIE bit and the I-bit in the Status Register are set (one), the Wake-up Timer interrupt is enabled. The corresponding interrupt is executed if a Wake-up Timer overflow occurs, i.e., when the WUTIF bit is set .RW0WUTRWake-up Timer ResetWhen WUTR is written to one, the Wake-up Timer is reset, and starts counting from zero. The WUTR bit is automatically cleared to zero after the reset has been performed.RW0WUTEWake-up Timer EnableWhen the WUTE is set (one) the Wake-up Timer is enabled, and the WUTE is cleared (zero) the Wake-up Timer function is disabled.RW0WUTP2Wake-up Timer Prescaler Bit 2The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.RW0WUTP1Wake-up Timer Prescaler Bit 1The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.RW0WUTP0Wake-up Timer Prescaler Bit 0The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.RW0[SIMULATOR2:JTAGICEmkII:AVRONE:STK600:STK500_2:STK500:AVRDragon]libATmega64HVE.dll0x9610DebugWire0x3f,0x00,0x60,0xf8,0xff,0xbf,0xb8,0xe00x3f,0x00,0x00,0xf8,0xff,0x1f,0xb8,0xe00X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000xdf,0xdb,0x00,0x40,0x37,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x03,0x1e,0x11,0xff,0xff,0x7f,0x000xdf,0xdb,0x00,0x40,0x33,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0xf7,0x03,0x1e,0x11,0xff,0xff,0x7f,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x000x570x000x800x040x7F000x7F000x7E000x7C000x78000xF60x100000x00,320x20,640x000x080x000x000x000x200xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF0xB6,0x01,0x110x3E0x3D0x310x000x000x000x7F000x000x3F0x9610DebugWire2001002532030x53111000x2112860x400x4C0x200xFF0x000x0464200xC00x000xA00xFF0xFF25625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00100060000151501050x0125625650x0725625605052001002532030x53112000x21128100x400x4C0x200xFF0x000x0464200xC00x000xA00xFF0xFF25625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00100060000151501050x0125625650x0725625605050xA01110xFF0xFF0xFF0