[PACKAGE:POWER:CORE:ADMIN:MEMORY:LOCKBIT:FUSE:PROGRAMMING:INTERRUPT_VECTOR:IO_MODULE:ICE_SETTINGS][TSOP;LGA]28[PV2][PV1][NV][GND][VFET][CF1P][CF1N][CF2P][CF2N][VREG][VREF][VREFGND][PI][NI][PA0][PA1][PA2][PB0][PB1][PB2][PB3][GND][VCC][PC0][BATT][GND][NC][OC]4MHz70CTBD mATBD mATBD uAV2EAVRSimCoreV2.SimCoreV2[][][]32$00$1B$1A$1D$1C$1F$1EATmega32HVB8MHZ1RELEASED$1E$95$1010x31000x003276810242048$100NANA$00$3F$60$FF$20$FFNA0xFE0x010x02NA0xFD0x010x020x040x080x100x20NA0xFC0x010x020x040x080x100x20NA0xFB0x010x020x040x080x100x20NA0xFA0x010x020x040x080x100x200x40NA0xF90x010x020x040x080x100x200x400x80NA0xF80x010x020x040x080x100x200x400x80NA0xF70x010x020x040x080x100x200x400x80NA0xF60x010x020x040x080x100x200x400x80NA0xF50x010x020x040x080x100x200x400x80NA0xF30x010x020x040x080x10NA0xF20x010x020x040x080x10NA0xF10x010x020x040x08NA0xF00x010x020x040x08NA0xEA0x010x020x040x080x100x200x400x80NA0xE90x010x020x040x080x100x200x400x80NA0xE80x01NA0xE70x010x020x040x100x200x40NA0xE60x010x020x040x080x100x200x400x80NA0xE50x010x020x040x080x100x200x400x80NA0xE40x010x020x040x080x100x200x400x80NA0xE30x010x020x040x080x100x200x400x80NA0xE20x010x020x040x080x100x200x400x80NA0xE10x010x020x040x080x100x200x400x80NA0xE00x010x020x040x080x100x200x400x80NA0xD40x010x020x040x080x10NA0xD20x010x020x100x20NA0xD10x010x020x040x080x100x200x400x80NA0xD00x010x020x040x080x100x20NA0xC80x010x020x100x80NA0xBE0x010x020x040x400x80NA0xBD0x020x040x080x100x200x400x80NA0xBC0x010x040x080x100x200x400x80NA0xBB0x010x020x040x080x100x200x400x80NA0xBA0x010x020x040x080x100x200x400x80NA0xB90x010x020x080x100x200x400x80NA0xB80x010x020x040x080x100x200x400x80NA0x890x010x020x040x080x100x200x400x80NA0x880x010x020x040x080x100x200x400x80NA0x850x010x020x040x080x100x200x400x80NA0x840x010x020x040x080x100x200x400x80NA0x810x010x020x04NA0x800x010x080x100x200x400x80NA0x7E0x010x02NA0x7C0x010x020x040x08NA0x7A0x010x020x040x08NA0x790x010x020x040x08NA0x780x010x020x040x080x100x200x400x80NA0x6F0x010x020x040x08NA0x6E0x010x020x040x08NA0x6C0x010x020x040x080x100x200x400x80NA0x6B0x010x020x040x08NA0x690x010x020x040x080x100x200x400x80NA0x680x010x02NA0x660x010x020x040x080x100x200x400x80NA0x640x010x020x040x080x200x40NA0x610x010x020x80NA0x600x010x020x040x080x100x200x400x800x3F0x5F0x010x020x040x080x100x200x400x800x3E0x5E0x080x010x020x040x080x100x200x400x800x3D0x5D0xff0x010x020x040x080x100x200x400x800x370x570x010x020x040x080x100x200x400x800x350x550x010x020x100x200x340x540x010x020x040x080x100x330x530x010x020x040x080x310x510x2e0x4e0x010x020x040x080x100x200x400x800x2d0x4d0x010x400x800x2c0x4c0x010x020x040x080x100x200x400x800x2B0x4B0x010x020x040x080x100x200x400x800x2A0x4A0x010x020x040x080x100x200x400x800x290x490x010x020x040x080x100x200x400x800x280x480x010x020x040x080x100x200x400x800x270x470x010x020x040x080x100x200x400x800x260x460x010x020x040x080x100x200x400x800x250x450x010x020x040x240x440x010x080x100x200x400x800x230x430x010x800x220x420x010x020x210x410x010x020x040x080x100x200x400x800x200x400x010x020x040x080x100x200x400x800x1F0x3F0x010x020x040x080x100x200x1E0x3E0x010x020x040x080x100x200x400x800x1D0x3D0x010x020x040x080x1C0x3C0x010x020x040x080x1B0x3B0x010x020x170x370x010x020x100x160x360x010x020x040x080x150x350x010x020x040x080x080x280x010x020x040x080x100x200x060x260x010x020x040x080x100x050x250x010x020x040x080x100x200x400x800x040x240x010x020x040x080x100x200x400x800x030x230x010x020x040x080x100x200x400x800x020x220x010x020x040x080x010x210x010x020x040x080x000x200x010x020x040x08$3800$3FFF$0000$37FF642564$0000$3F00$3F005128$0000$3E00$3E00102416$0000$3C00$3C00204832$0000$3800$3800[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled6110x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabled0x0C0x0CApplication Protection Mode 1: No lock on SPM and LPM in Application Section0x0C0x08Application Protection Mode 2: SPM prohibited in Application Section0x0C0x00Application Protection Mode 3: LPM and SPM prohibited in Application Section0x0C0x04Application Protection Mode 4: LPM prohibited in Application Section0x300x30Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section0x300x20Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section0x300x00Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section0x300x10Boot Loader Protection Mode 4: LPM prohibited in Boot Loader SectionLB1Lock bitLB2Lock bitBLB01Boot Lock bitBLB02Boot Lock bitBLB11Boot lock bitBLB12Boot lock bit[LOW:HIGH]8WDTONWatchdog Timer Always On1EESAVEEEPROM memory is preserved through chip erase1SPIENEnable Serial programming and Data Downloading0SUT2Select start-up time1SUT1Select start-up time1SUT0Select start-up time1OSCSEL1Oscillator Select1OSCSEL0Oscillator Select0130x800x00Watch-dog Timer always on; [WDTON=0]0x400x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x200x00Serial program downloading (SPI) enabled; [SPIEN=0]0x01C0x00Start-up time 14 CK + 4 ms; [SUT=000]0x01C0x01Start-up time 14 CK + 8 ms; [SUT=001]0x01C0x02Start-up time 14 CK + 16 ms; [SUT=010]0x01C0x03Start-up time 14 CK + 32 ms; [SUT=011]0x01C0x04Start-up time 14 CK + 64 ms; [SUT=100]0x01C0x05Start-up time 14 CK + 128 ms; [SUT=101]0x01C0x06Start-up time 14 CK + 256 ms; [SUT=110]0x1C0x07Start-up time 14 CK + 512 ms; [SUT=111]; default value5DUVRDINITReset Value of DUVRDRegister0DWENEnable debugWire1BOOTSZ1Select Boot Size0BOOTSZ0Select Boot Size0BOOTRSTSelect Reset Vector170x100x00DUVR mode on; [DUVR=0]0x080x00Debug Wire enable; [DWEN=0]0x060x06Boot Flash section size=256 words Boot start address=$3F00; [BOOTSZ=11]0x060x04Boot Flash section size=512 words Boot start address=$3E00; [BOOTSZ=10]0x060x02Boot Flash section size=1024 words Boot start address=$3C00; [BOOTSZ=01]0x060x00Boot Flash section size=2048 words Boot start address=$3800; [BOOTSZ=00] ; default value0x010x00Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]0xff,0xdf0xff,0xdf0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x08,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x08,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!0x00,8.0 MHz128429$0000RESETExternal Pin, Power-on Reset, Brown-out Reset and Watchdog Reset$0002BPINTBattery Protection Interrupt$0004VREGMONVoltage regulator monitor interrupt$0006INT0External Interrupt Request 0$0008INT1External Interrupt Request 1$000AINT2External Interrupt Request 2$000CINT3External Interrupt Request 3$000EPCINT0Pin Change Interrupt 0$0010PCINT1Pin Change Interrupt 1$0012WDTWatchdog Timeout Interrupt$0014BGSCDBandgap Buffer Short Circuit Detected$0016CHDETCharger Detect$0018TIMER1_ICTimer 1 Input capture$001ATIMER1_COMPATimer 1 Compare Match A$001CTIMER1_COMPBTimer 1 Compare Match B$001ETIMER1_OVFTimer 1 overflow$0020TIMER0_ICTimer 0 Input Capture$0022TIMER0_COMPATimer 0 Comapre Match A$0024TIMER0_COMPBTimer 0 Compare Match B$0026TIMER0_OVFTimer 0 Overflow$0028TWIBUSCDTwo-Wire Bus Connect/Disconnect$002ATWITwo-Wire Serial Interface$002CSPI_STCSPI Serial transfer complete$002EVADCVoltage ADC Conversion Complete$0030CCADC_CONVCoulomb Counter ADC Conversion Complete$0032CCADC_REG_CURColoumb Counter ADC Regular Current$0034CCADC_ACCColoumb Counter ADC Accumulator$036EE_READYEEPROM Ready$038SPMSPM Ready[AD_CONVERTER:WATCHDOG:FET:SPI:EEPROM:COULOMB_COUNTER:TWI:EXTERNAL_INTERRUPT:TIMER_COUNTER_1:CELL_BALANCING:BATTERY_PROTECTION:CHARGER_DETECT:VOLTAGE_REGULATOR:BANDGAP:CPU:PORTA:PORTB:PORTC:TIMER_COUNTER_0:BOOT_LOAD][VADMUX:VADCH:VADCL:VADCSR]
[VADCH:VADCL]
io_analo.bmp12-bit resolution Sigmal-Delta ADC with +/-1 LSB Accuracy. 512 us conversion time.VADMUXThe VADC multiplexer Selection RegisterNA0x7Cio_analo.bmpYVADMUX3Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0VADMUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0VADMUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0VADMUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0VADCHVADC Data Register High ByteWhen VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH.NA0x79io_analo.bmpNVADC11ADC Data Register High Byte Bit 3R0VADC10ADC Data Register High Byte Bit 2R0VADC9ADC Data Register High Byte Bit 1R0VADC8ADC Data Register High Byte Bit 0R0VADCLVADC Data Register Low ByteWhen VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH.NA0x78io_analo.bmpNVADC7ADC Data Register Low Byte Bit 7R0VADC6ADC Data Register Low Byte Bit 6R0VADC5ADC Data Register Low Byte Bit 5R0VADC4ADC Data Register Low Byte Bit 4R0VADC3ADC Data Register Low Byte Bit 3R0VADC2ADC Data Register Low Byte Bit 2R0VADC1ADC Data Register Low Byte Bit 1R0VADC0ADC Data Register Low Byte Bit 0R0VADCSRThe VADC Control and Status registerNA0x7Aio_flag.bmpYVADENVADC EnableWriting this bit to one enables V-ADC Conversion. By writing it to zero, the V-ADC is turned off. Turning the V-ADC off while a conversion is in progress will terminate this conversionRW0VADSCVADC Satrt ConversionWrite this bit to one to start a new conversion of the selected channel. VADSC will read as one as long as the conversion is not finished. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect.RW0VADCCIFVADC Conversion Complete Interrupt FlagThis bit is set when a V-ADC conversion completes and the data registers are updated.V-ADC Conversion complete Interrupt is executed if the VADCCIE bit and the I-bit in S-REG are set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on VADCSR, a pending interrupt can be disabled.RW0VADCCIEVADC Conversion Complete Interrupt EnableWhen this bit is written to one and the I-Bit in SREG is set, the V-ADC Conversion Complete Interrupt is activatedRW0[WDTCSR]io_watch.bmpWDTCSRWatchdog Timer Control RegisterNA0x60io_flag.bmpYWDIFWatchdog Timeout Interrupt FlagRW0WDIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2WDOG_TIMER_PRESCALE_4BITSRW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[FCSR]io_analo.bmpFCSRFET Control and Status RegisterNA0xF0io_analo.bmpYDUVRDDeep Under-Voltage Recovery DisableRW0CPSCurrent Protection StatusThe CPTS bit shows the status of the Current Protection. This bit is set (one) when the Current Protection Timer is activated, and is cleared (zero) when the hold-off time has elapsed. RW0DFEDischarge FET EnableWhen the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Discharge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). RW0CFECharge FET EnableWhen the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Charge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). RW0[SPDR:SPSR:SPCR]io_com.bmpThe Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)SPCRSPI Control Register0x2c0x4cio_flag.bmpYSPIESPI Interrupt EnableThis bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.RW0SPESPI EnableWhen the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.RW0DORDData OrderWhen the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.RW0MSTRMaster/Slave SelectThis bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.RW0CPOLClock polarityWhen this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.RW0CPHAClock PhaseRefer to Figure 36 or Figure 37 for the functionality of this bit.RW0SPR1SPI Clock Rate Select 1These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RW0SPR0SPI Clock Rate Select 0These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RWCOMM_SCK_RATE_3BIT0SPSRSPI Status Register0x2d0x4dio_flag.bmpYSPIFSPI Interrupt FlagWhen a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).R0WCOLWrite Collision FlagThe WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.R0SPI2XDouble SPI Speed BitWhen this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading. RW0SPDRSPI Data RegisterThe SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.0x2e0x4eio_com.bmpNSPDR7SPI Data Register bit 7RWXSPDR6SPI Data Register bit 6RWXSPDR5SPI Data Register bit 5RWXSPDR4SPI Data Register bit 4RWXSPDR3SPI Data Register bit 3RWXSPDR2SPI Data Register bit 2RWXSPDR1SPI Data Register bit 1R0SPDR0SPI Data Register bit 0R0[EEARH:EEARL:EEDR:EECR]
[EEARH:EEARL]
io_cpu.bmpEEPROM_m32HVB.xmlEEARHEEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction0x220x42io_cpu.bmpNEEAR9EEPROM Read/Write Access bit 9RW0EEAR8EEPROM Read/Write Access bit 8RW0EEARLEEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction0x210x41io_cpu.bmpNEEAR7EEPROM Read/Write Access bit 7RW0EEAR6EEPROM Read/Write Access bit 6RW0EEAR5EEPROM Read/Write Access bit 5RW0EEAR4EEPROM Read/Write Access bit 4RW0EEAR3EEPROM Read/Write Access bit 3RW0EEAR2EEPROM Read/Write Access bit 2RW0EEAR1EEPROM Read/Write Access bit 1RW0EEAR0EEPROM Read/Write Access bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.0x200x40io_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register0x1F0x3Fio_flag.bmpYEEPM1RW0EEPM0RWEEP_MODE0EERIEEEProm Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).RW0EEMPEEEMWEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.RW0EEPEEEWEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.RW0EEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.RW0[CADCSRA:CADCSRB:CADCSRC:CADICH:CADICL:CADAC3:CADAC2:CADAC1:CADAC0:CADRCC:CADRDC]
[CADICH:CADICL];[CADAC3:CADAC2:CADAC1:CADAC0]
io_analo.bmpCoulombCounter_m406CADCSRACC-ADC Control and Status Register ANA0xE6io_analo.bmpYCADENWhen the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW0CADPOLRW0CADUBCC_ADC Update BusyRW0CADAS1CC_ADC Accumulate Current Select Bit 1The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.RW0CADAS0CC_ADC Accumulate Current Select Bit 0The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.RW0CADSI1The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADSI0The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADSEWhen the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.RW0CADCSRBCC-ADC Control and Status Register BNA0xE7io_analo.bmpYCADACIECC-ADC Accumulate Current Interrupt Enable RW0CADRCIERegular Current Interrupt EnableWhen the CADACIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Accumulate Current Interrupt is enabled. RW0CADICIECAD Instantenous Current Interrupt EnableThe CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADACIFCC-ADC Accumulate Current Interrupt FlagThe CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.RW0CADRCIFCC-ADC Accumulate Current Interrupt FlagThe CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.RW0CADICIFCC-ADC Instantaneous Current Interrupt Flag The CADICIF bit is set (one) when a CC-ADC Instantaneous Current conversion is completed. The CC-ADC Instantaneous Current Interrupt is executed if the CADICIE bit and the I-bit in SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag. RW0CADCSRCCC-ADC Control and Status Register CNA0xE8io_analo.bmpYCADVSECC-ADC Voltage Scaling EnableSetting this flag enables the Internal Voltage Scaling.RW0CADICHCC-ADC Instantaneous CurrentNA0xE5io_analo.bmpNCADICH7When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW0CADICH6RW0CADICH5RW0CADICH4The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADICH3The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADICH2The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADICH1The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADICH0When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.RW0CADICLCC-ADC Instantaneous CurrentNA0xE4io_analo.bmpNCADICL7When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW0CADICL6RW0CADICL5RW0CADICL4The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADICL3The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADICL2The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADICL1The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADICL0When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.RW0CADAC3ADC Accumulate CurrentNA0xE3io_analo.bmpNCADAC31R0CADAC30R0CADAC29R0CADAC28R0CADAC27R0CADAC26R0CADAC25R0CADAC24R0CADAC2ADC Accumulate CurrentNA0xE2io_analo.bmpNCADAC23R0CADAC22R0CADAC21R0CADAC20R0CADAC19R0CADAC18R0CADAC17R0CADAC16R0CADAC1ADC Accumulate CurrentNA0xE1io_analo.bmpNCADAC15R0CADAC14R0CADAC13R0CADAC12R0CADAC11R0CADAC10R0CADAC09R0CADAC08R0CADAC0ADC Accumulate CurrentNA0xE0io_analo.bmpNCADAC07R0CADAC06R0CADAC05R0CADAC04R0CADAC03R0CADAC02R0CADAC01R0CADAC00R0CADRCCCC-ADC Regular Charge CurrentThe CC-ADC Regular Charge Current Register determines the threshold level for the Regular Charge CurrentNA0xE9io_analo.bmpNCADRCC7RW0CADRCC6RW0CADRCC5RW0CADRCC4RW0CADRCC3RW0CADRCC2RW0CADRCC1RW0CADRCC0RW0CADRDCCC-ADC Regular Discharge Currenthe CC-ADC Regular Current Discharge Register determines the threshold level for the Regular Discharge CurrentNA0xEAio_analo.bmpNCADRDC7RW0CADRDC6RW0CADRDC5RW0CADRDC4RW0CADRDC3RW0CADRDC2RW0CADRDC1RW0CADRDC0RW0[TWBCSR:TWAMR:TWBR:TWCR:TWSR:TWDR:TWAR]io_com.bmpTWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI TWBCSRTWI Bus Control and Status RegisterThe Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configuration bit, an interrupt can be generated either when the TWI bus is connected or disconnected.NA0xBEio_com.bmpYTWBCIFTWI Bus Connect/Disconnect Interrupt FlagRW0TWBCIETWI Bus Connect/Disconnect Interrupt EnableRW0TWBDT1TWI Bus Disconnect Time-out PeriodRWCOMM_TW_BUS_TIMEOUT0TWBDT0TWI Bus Disconnect Time-out PeriodRW0TWBCIPTWI Bus Connect/Disconnect Interrupt PolarityRW0TWAMRTWI (Slave) Address Mask RegisterThe TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ingnores the compare between the incomming address bit and the corresponding bit in TWAR.NA0xBDio_com.bmpYTWAM6RW0TWAM5RW0TWAM4RW0TWAM3RW0TWAM2RW0TWAM1RW0TWAM0RW0TWBRTWI Bit Rate registerTWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.NA0xB8io_com.bmpNTWBR7RW0TWBR6RW0TWBR5RW0TWBR4RW0TWBR3RW0TWBR2RW0TWBR1RW0TWBR0RW0TWCRTWI Control RegisterThe TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.NA0xBCio_flag.bmpYTWINTTWI Interrupt FlagThis bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flagRW0TWEATWI Enable Acknowledge BitThe TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one againRW0TWSTATWI Start Condition BitThe application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.RW0TWSTOTWI Stop Condition BitWriting the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.RW0TWWCTWI Write Collition FlagThe TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.RW0TWENTWI Enable BitThe TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.RW0TWIETWI Interrupt EnableWhen this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.RW0TWSRTWI Status RegisterNA0xB9io_flag.bmpYTWS7TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient cRW0TWS6TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWS5TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient cRW0TWS4TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWS3TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWPS1TWI PrescalerBits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.RW0TWPS0TWI PrescalerBits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.RWCOMM_TWI_PRESACLE0TWDRTWI Data registerIn transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directlNA0xBBio_com.bmpNTWD7TWI Data Register Bit 7RW1TWD6TWI Data Register Bit 6RW1TWD5TWI Data Register Bit 5RW1TWD4TWI Data Register Bit 4RW1TWD3TWI Data Register Bit 3RW1TWD2TWI Data Register Bit 2RW1TWD1TWI Data Register Bit 1RW1TWD0TWI Data Register Bit 0RW1TWARTWI (Slave) Address registerThe TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generaNA0xBAio_com.bmpYTWA6TWI (Slave) Address register Bit 6RW0TWA5TWI (Slave) Address register Bit 5RW0TWA4TWI (Slave) Address register Bit 4RW0TWA3TWI (Slave) Address register Bit 3RW0TWA2TWI (Slave) Address register Bit 2RW0TWA1TWI (Slave) Address register Bit 1RW0TWA0TWI (Slave) Address register Bit 0RW0TWGCETWI General Call Recognition Enable BitRW0[EICRA:EIMSK:EIFR:PCICR:PCIFR:PCMSK1:PCMSK0]
[PCMSK1:PCMSK0]
io_ext.bmpThe external interrupts are triggered by the INT3:0 pins or any of the PCINT11:0 pins.EICRAExternal Interrupt Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.NA0x69io_flag.bmpYISC31External Interrupt Sense Control 3 Bit 1 RW0ISC30External Interrupt Sense Control 3 Bit 0RWINTERRUPT_SENSE_CONTROL0ISC21External Interrupt Sense Control 2 Bit 1RW0ISC20External Interrupt Sense Control 2 Bit 0RWINTERRUPT_SENSE_CONTROL0ISC11External Interrupt Sense Control 1 Bit 1 RW0ISC10External Interrupt Sense Control 1 Bit 0RWINTERRUPT_SENSE_CONTROL0ISC01External Interrupt Sense Control 0 Bit 1 RW0ISC00External Interrupt Sense Control 0 Bit 0RWINTERRUPT_SENSE_CONTROL0EIMSKExternal Interrupt Mask Register0x1D0x3Dio_flag.bmpYINT3External Interrupt Request 3 EnableRW0INT2External Interrupt Request 2 EnableRW0INT1External Interrupt Request 1 EnableRW0INT0External Interrupt Request 0 EnableRW0EIFRExternal Interrupt Flag Register0x1C0x3Cio_flag.bmpYINTF3External Interrupt Flag 3RW0INTF2External Interrupt Flag 2RW0INTF1External Interrupt Flag 1RW0INTF0External Interrupt Flag 0RW0PCICRPin Change Interrupt Control RegisterNA0x68io_flag.bmpYPCIE1Pin Change Interrupt Enable 1RW0PCIE0Pin Change Interrupt Enable 0RW0PCIFRPin Change Interrupt Flag Register0x1B0x3Bio_flag.bmpYPCIF1Pin Change Interrupt Flag 1RW0PCIF0Pin Change Interrupt Flag 1RW0PCMSK1Pin Change Enable Mask Register 1NA0x6Cio_flag.bmpNPCINT11Pin Change Enable Mask 11RW0PCINT10Pin Change Enable Mask 10RW0PCINT9Pin Change Enable Mask 9RW0PCINT8Pin Change Enable Mask 8RW0PCINT7Pin Change Enable Mask 7RW0PCINT6Pin Change Enable Mask 6RW0PCINT5Pin Change Enable Mask 5RW0PCINT4Pin Change Enable Mask 4RW0PCMSK0Pin Change Enable Mask Register 0NA0x6Bio_flag.bmpNPCINT3Pin Change Enable Mask 3RW0PCINT2Pin Change Enable Mask 2RW0PCINT1Pin Change Enable Mask 1RW0PCINT0Pin Change Enable Mask 0RW0[TCCR1A:TCCR1B:TCNT1H:TCNT1L:OCR1A:OCR1B:TIMSK1:TIFR1:GTCCR]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL]
io_timer.bmpTCCR1BTimer/Counter1 Control Register BNA0x81io_flag.bmpYCS12Clock Select1 bit 2RW0CS11Clock Select1 bit 1RW0CS10Clock Select1 bit 0RWCLK_SEL_3BIT_EXT0TCCR1ATimer/Counter 1 Control Register ANA0x80io_flag.bmpYTCW1Timer/Counter WidthWhen this bit is written to one 16-bit mode is selected. RW0ICEN1Input Capture Mode EnableThe Input Capture Mode is enabled when this bit is written to one.RW0ICNC1Input Capture Noise CancelerSetting this bit activates the Input Capture Noise Canceler. RW0ICES1Input Capture Edge SelectThis bit selects which edge on the Input Capture Source that is used to trigger a capture event.RW0ICS1Input Capture SelectWhen written logic one, this bit enables the input capture function in Timer/Counter to be triggered by the alternative Input Capture Source.RW0WGM10Waveform Generation ModeThis bit controls the counting sequence of the counterRW0TCNT1HTimer Counter 1 High ByteNA0x85io_timer.bmpNTCNT1H7Timer Counter 1 High Byte bit 7RW0TCNT1H6Timer Counter 1 High Byte bit 6RW0TCNT1H5Timer Counter 1 High Byte bit 5RW0TCNT1H4Timer Counter 1 High Byte bit 4RW0TCNT1H3Timer Counter 1 High Byte bit 3RW0TCNT1H2Timer Counter 1 High Byte bit 2RW0TCNT1H1Timer Counter 1 High Byte bit 1RW0TCNT1H0Timer Counter 1 High Byte bit 0RW0TCNT1LTimer Counter 1 Low ByteNA0x84io_timer.bmpNTCNT1L7Timer Counter 1 Low Byte bit 7RW0TCNT1L6Timer Counter 1 Low Byte bit 6RW0TCNT1L5Timer Counter 1 Low Byte bit 5RW0TCNT1L4Timer Counter 1 Low Byte bit 4RW0TCNT1L3Timer Counter 1 Low Byte bit 3RW0TCNT1L2Timer Counter 1 Low Byte bit 2RW0TCNT1L1Timer Counter 1 Low Byte bit 1RW0TCNT1L0Timer Counter 1 Low Byte bit 0RW0OCR1AOutput Compare Register 1A The Output Compare Register A contains an 8-bit value that is continuously compared with theNA0x88io_timer.bmpNOCR1A7RW0OCR1A6RW0OCR1A5RW0OCR1A4RW0OCR1A3RW0OCR1A2RW0OCR1A1RW0OCR1A0RW0OCR1BOutput Compare Register B NA0x89io_timer.bmpNOCR1B7RW0OCR1B6RW0OCR1B5RW0OCR1B4RW0OCR1B3RW0OCR1B2RW0OCR1B1RW0OCR1B0RW0TIMSK1Timer/Counter Interrupt Mask RegisterNA0x6Fio_flag.bmpYICIE1Timer/Counter n Input Capture Interrupt EnableRW0OCIE1BTimer/Counter1 Output Compare B Interrupt EnableRW0OCIE1ATimer/Counter1 Output Compare A Interrupt EnableRW0TOIE1Timer/Counter1 Overflow Interrupt EnableRW0TIFR1Timer/Counter Interrupt Flag register0x160x36io_flag.bmpYICF1Timer/Counter 1 Input Capture FlagRW0OCF1BTimer/Counter1 Output Compare Flag BRW0OCF1ATimer/Counter1 Output Compare Flag ARW0TOV1Timer/Counter1 Overflow FlagRW0GTCCRGeneral Timer/Counter Control Register0x230x43io_flag.bmpYTSMTimer/Counter Synchronization ModeRW0PSRSYNCPrescaler ResetRW0[CBCR]io_analo.bmpCBCRCell Balancing Control RegisterNA0xF1io_analo.bmpYCBE4Cell Balancing Enable 4RW0CBE3Cell Balancing Enable 4RW0CBE2Cell Balancing Enable 2RW0CBE1Battery Protection Parameter LockRW0[BPPLR:BPCR:BPHCTR:BPOCTR:BPSCTR:BPCHCD:BPDHCD:BPCOCD:BPDOCD:BPSCD:BPIFR:BPIMSK]io_analo.bmpBPPLRBattery Protection Parameter Lock RegisterNA0xFEio_analo.bmpYBPPLEBattery Protection Parameter Lock EnableRW0BPPLBattery Protection Parameter LockRW0BPCRBattery Protection Control RegisterNA0xFDio_analo.bmpYEPIDExternal Protection Input DisableRW0SCDShort Circuit Protection DisabledRW0DOCDDischarge Over-current Protection DisabledRW0COCDCharge Over-current Protection DisabledRW0DHCDDischarge High-current Protection DisableRW0CHCDCharge High-current Protection DisableRW0BPHCTRBattery Protection Short-current Timing RegisterNA0xFCio_analo.bmpNHCPT5High-current Protection Timing bit 5RW0HCPT4High-current Protection Timing bit 4RW0HCPT3High-current Protection Timing bit 3RW0HCPT2High-current Protection Timing bit 2RW0HCPT1High-current Protection Timing bit 1RW0HCPT0High-current Protection Timing bit 0RW0BPOCTRBattery Protection Over-current Timing RegisterNA0xFBio_analo.bmpNOCPT5Over-current Protection Timing bit 5These bits control the delay of the Over-circuit Protection. RW0OCPT4Over-current Protection Timing bit 4These bits control the delay of the Over-circuit Protection. RW0OCPT3Over-current Protection Timing bit 3These bits control the delay of the Over-circuit Protection. RW0OCPT2Over-current Protection Timing bit 2These bits control the delay of the Over-circuit Protection. RW0OCPT1Over-current Protection Timing bit 1These bits control the delay of the Over-circuit Protection. RW1OCPT0Over-current Protection Timing bit 0These bits control the delay of the Over-circuit Protection. RW0BPSCTRBattery Protection Short-current Timing RegisterNA0xFAio_analo.bmpNSCPT6Short-current Protection TimingRW0SCPT5Short-current Protection TimingRW0SCPT4Short-current Protection TimingRW1SCPT3Short-current Protection TimingRW0SCPT2Short-current Protection TimingRW0SCPT1Short-current Protection TimingRW0SCPT0Short-current Protection TimingRW0BPCHCDBattery Protection Charge-High-current Detection Level RegisterNA0xF9io_analo.bmpNCHCDL7Charge High-current Detection LevelThese bits sets the RSENSE voltage level for detection of Charge High-currentRW1CHCDL6Charge High-current Detection LevelThese bits sets the RSENSE voltage level for detection of Charge High-currentRW1CHCDL5Charge High-current Detection LevelThese bits sets the RSENSE voltage level for detection of Charge High-currentRW0CHCDL4Charge High-current Detection LevelThese bits sets the RSENSE voltage level for detection of Charge High-currentRW0CHCDL3Charge High-current Detection LevelThese bits sets the RSENSE voltage level for detection of Charge High-currentRW1CHCDL2Charge High-current Detection LevelThese bits sets the RSENSE voltage level for detection of Charge High-currentRW1CHCDL1Charge High-current Detection LevelThese bits sets the RSENSE voltage level for detection of Charge High-currentRW1CHCDL0Charge High-current Detection LevelThese bits sets the RSENSE voltage level for detection of Charge High-currentRW1BPDHCDBattery Protection Discharge-High-current Detection Level RegisterNA0xF8io_analo.bmpNDHCDL7Discharge High-current Detection Level bit 7RW1DHCDL6Discharge High-current Detection Level bit 6RW1DHCDL5Discharge High-current Detection Level bit 5RW1DHCDL4Discharge High-current Detection Level bit 4RW1DHCDL3Discharge High-current Detection Level bit 3RW0DHCDL2Discharge High-current Detection Level bit 2RW0DHCDL1Discharge High-current Detection Level bit 1RW1DHCDL0Discharge High-current Detection Level bit 01RWBPCOCDBattery Protection Charge-Over-current Detection Level RegisterNA0xF7io_analo.bmpNCOCDL7Charge Over-current Detection LevelRW1COCDL6Charge Over-current Detection LevelRW1COCDL5Charge Over-current Detection LevelRW1COCDL4Charge Over-current Detection LevelRW1COCDL3Charge Over-current Detection LevelRW0COCDL2Charge Over-current Detection LevelRW0COCDL1Charge Over-current Detection LevelRW1COCDL0Charge Over-current Detection LevelRW1BPDOCDBattery Protection Discharge-Over-current Detection Level RegisterNA0xF6io_analo.bmpNDOCDL7Discharge Over-current Detection Level bit7RW1DOCDL6Discharge Over-current Detection Level bit6RW1DOCDL5Discharge Over-current Detection Level bit5RW1DOCDL4Discharge Over-current Detection Level bit4RW1DOCDL3Discharge Over-current Detection Level bit3RW0DOCDL2Discharge Over-current Detection Level bit2RW0DOCDL1Discharge Over-current Detection Level bit1RW1DOCDL0Discharge Over-current Detection Level bit0RW1BPSCDBattery Protection Short-Circuit Detection Level RegisterNA0xF5io_analo.bmpNSCDL7Short-circuit Detection Level bit 7RW1SCDL6Short-circuit Detection Level bit 6RW1SCDL5Short-circuit Detection Level bit 5RW1SCDL4Short-circuit Detection Level bit 4RW1SCDL3Short-circuit Detection Level bit 3RW0SCDL2Short-circuit Detection Level bit 2RW0SCDL1Short-circuit Detection Level bit 1RW1SCDL0Short-circuit Detection Level bit 0RW1BPIFRBattery Protection Interrupt Flag RegisterNA0xF3io_analo.bmpYSCIFShort-circuit Protection Activated Interrupt FlagRW0DOCIFDischarge Over-current Protection Activated Interrupt FlagRW0COCIFCharge Over-current Protection Activated Interrupt FlagRW0DHCIFDisharge High-current Protection Activated InterruptRW0CHCIFCharge High-current Protection Activated InterruptRW0BPIMSKBattery Protection Interrupt Mask RegisterNA0xF2io_analo.bmpYSCIEShort-circuit Protection Activated Interrupt EnableRW0DOCIEDischarge Over-current Protection Activated Interrupt EnableRW0COCIECharge Over-current Protection Activated Interrupt EnableRW0DHCIEDischarger High-current Protection Activated InterruptRW0CHCIECharger High-current Protection Activated InterruptRW0[CHGDCSR]io_analo.bmpCHGDCSRCharger Detect Control and Status RegisterNA0xD4io_analo.bmpYBATTPVLBATT Pin Voltage LevelRW0CHGDISC1Charger Detect Interrupt Sense ControlRW0CHGDISC0Charger Detect Interrupt Sense ControlRW0CHGDIFCharger Detect Interrupt FlagRW0CHGDIECharger Detect Interrupt EnableRW0[ROCR]io_analo.bmpROCRRegulator Operating Condition RegisterNA0xC8io_analo.bmpYROCSROC StatusR0ROCDROC DisableR0ROCWIFROC Warning Interrupt FlagRW0ROCWIEROC Warning Interrupt EnableRW0[BGCSR:BGCRR:BGCCR]io_analo.bmpBGCSRBandgap Control and Status RegisterNA0xD2io_analo.bmpYBGDBandgap DisableRW0BGSCDEBandgap Short Circuit Detection EnabledRW0BGSCDIFBandgap Short Circuit Detection Interrupt FlagRW0BGSCDIEBandgap Short Circuit Detection Interrupt EnableRW0BGCRRBandgap Calibration of Resistor LadderNA0xD1io_analo.bmpNBGCR7Bandgap Calibration of Resistor Ladder Bit 7RW0BGCR6Bandgap Calibration of Resistor Ladder Bit 6RW0BGCR5Bandgap Calibration of Resistor Ladder Bit 5RW0BGCR4Bandgap Calibration of Resistor Ladder Bit 4RW0BGCR3Bandgap Calibration of Resistor Ladder Bit 3RW0BGCR2Bandgap Calibration of Resistor Ladder Bit 2RW0BGCR1Bandgap Calibration of Resistor Ladder Bit 1RW0BGCR0Bandgap Calibration of Resistor Ladder Bit 0RW0BGCCRBandgap Calibration RegisterNA0xD0io_analo.bmpYBGCC5BG Calibration of PTAT Current Bit 5RW0BGCC4BG Calibration of PTAT Current Bit 4These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0BGCC3BG Calibration of PTAT Current Bit 3These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0BGCC2BG Calibration of PTAT Current Bit 2These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0BGCC1BG Calibration of PTAT Current Bit 1These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0BGCC0BG Calibration of PTAT Current Bit 0These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0[SREG:SPH:SPL:MCUCR:MCUSR:FOSCCAL:OSICSR:SMCR:GPIOR2:GPIOR1:GPIOR0:DIDR0:PRR0:CLKPR]
[SPH:SPL]
io_cpu.bmpSREGStatus Register0x3F0x5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPHStack Pointer High0x3E0x5Eio_sph.bmpNSP15Stack pointer bit 15RW0SP14Stack pointer bit 14RW0SP13Stack pointer bit 13RW0SP12Stack pointer bit 12RW0SP11Stack pointer bit 11RW0SP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW0SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D0x5Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.0x350x55io_flag.bmpYCKOEClock Output EnableWhen this bit is written to one, the CPU clock divided by 4 is output on the CKOUT pin. The CKOUT pin will be tri-stated when this bit is zero.RW0PUDPull-up disableWhen this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). RW0IVSELInterrupt Vector SelectRW0IVCEInterrupt Vector Change EnableRW0MCUSRMCU Status RegisterThe MCU Status Register provides information on which reset source caused an MCU reset.0x340x54io_flag.bmpYOCDRFOCD Reset FlagRW0WDRFWatchdog Reset FlagThis bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.RW0BODRFBrown-out Reset FlagThis bit is set if a Brown-out Reset occurs. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.RW0EXTRFExternal Reset FlagThis bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.RW0PORFPower-on reset flagThis bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.RW0FOSCCALFast Oscillator Calibration ValueWriting the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table NA0x66io_cpu.bmpNFCAL7Oscillator Calibration Value Bit7RW0FCAL6Oscillator Calibration Value Bit6RW0FCAL5Oscillator Calibration Value Bit5RW0FCAL4Oscillator Calibration Value Bit4RW0FCAL3Oscillator Calibration Value Bit3RW0FCAL2Oscillator Calibration Value Bit2RW0FCAL1Oscillator Calibration Value Bit1RW0FCAL0Oscillator Calibration Value Bit0RW0OSICSROscillator Sampling Interface Control and Status Register0x170x37io_cpu.bmpYOSISEL0Oscillator Sampling Interface Select 0RW0OSISTOscillator Sampling Interface StatusR0OSIENOscillator Sampling Interface EnableRW0SMCRSleep Mode Control RegisterThe Sleep Mode Control Register contains control bits for power management.0x330x53io_cpu.bmpYSM2Sleep Mode Select bit 2These bits select between the five available sleep modes.RW0SM1Sleep Mode Select bit 1These bits select between the five available sleep modes.RW0SM0Sleep Mode Select bit 0These bits select between the five available sleep modes.RW0SESleep EnableThe SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.ToRW0GPIOR2General Purpose IO Register 2The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2B0x4Bio_cpu.bmpNGPIOR27General Purpose IO Register 2 bit 7RW0GPIOR26General Purpose IO Register 2 bit 6RW0GPIOR25General Purpose IO Register 2 bit 5RW0GPIOR24General Purpose IO Register 2 bit 4RW0GPIOR23General Purpose IO Register 2 bit 3RW0GPIOR22General Purpose IO Register 2 bit 2RW0GPIOR21General Purpose IO Register 2 bit 1RW0GPIOR20General Purpose IO Register 2 bit 0RW0GPIOR1General Purpose IO Register 1The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2A0x4Aio_cpu.bmpNGPIOR17General Purpose IO Register 1 bit 7RW0GPIOR16General Purpose IO Register 1 bit 6RW0GPIOR15General Purpose IO Register 1 bit 5RW0GPIOR14General Purpose IO Register 1 bit 4RW0GPIOR13General Purpose IO Register 1 bit 3RW0GPIOR12General Purpose IO Register 1 bit 2RW0GPIOR11General Purpose IO Register 1 bit 1RW0GPIOR10General Purpose IO Register 1 bit 0RW0GPIOR0General Purpose IO Register 0The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x1E0x3Eio_cpu.bmpNGPIOR07General Purpose IO Register 0 bit 7RW0GPIOR06General Purpose IO Register 0 bit 6RW0GPIOR05General Purpose IO Register 0 bit 5RW0GPIOR04General Purpose IO Register 0 bit 4RW0GPIOR03General Purpose IO Register 0 bit 3RW0GPIOR02General Purpose IO Register 0 bit 2RW0GPIOR01General Purpose IO Register 0 bit 1RW0GPIOR00General Purpose IO Register 0 bit 0RW0DIDR0Digital Input Disable RegisterNA0x7Eio_cpu.bmpYPA1DIDWhen this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.RW0PA0DIDWhen this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.RW0PRR0Power Reduction Register 0NA0x64io_cpu.bmpYPRTWIPower Reduction TWIRW0PRVRMPower Reduction Voltage Regulator MonitorRW0PRSPIPower reduction SPIRW0PRTIM1Power Reduction Timer/Counter1Writing a logic one to this bit shuts down the Timer/Counter1 module. When the, Timer/Counter1 is enabled, operation will continue like before the shutdown.RW0PRTIM0Power Reduction Timer/Counter0Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.RW0PRVADCPower Reduction V-ADCWriting a logic one to this bit shuts down the V-ADC. The V-ADC must be disabled before shut down.RW0CLKPRClock Prescale RegisterNA0x61io_cpu.bmpYCLKPCEClock Prescaler Change EnableRW0CLKPS1Clock Prescaler Select Bit 1RW1CLKPS0Clock Prescaler Select Bit 0RW1[PORTA:DDRA:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTAPort A Data Register0x020x22io_port.bmpNPORTA3Port A Data Register bit 3RW0PORTA2Port A Data Register bit 2RW0PORTA1Port A Data Register bit 1RW0PORTA0Port A Data Register bit 0RW0DDRAPort A Data Direction Register0x010x21io_flag.bmpNDDA3Data Direction Register, Port A, bit 3RW0DDA2Data Direction Register, Port A, bit 2RW0DDA1Data Direction Register, Port A, bit 1RW0DDA0Data Direction Register, Port A, bit 0RW0PINAPort A Input PinsThe Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.0x000x20io_port.bmpNPINA3Input Pins, Port A bit 3RWHi-ZPINA2Input Pins, Port A bit 2RWHi-ZPINA1Input Pins, Port A bit 1RWHi-ZPINA0Input Pins, Port A bit 0RWHi-Z[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register0x050x25io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register0x040x24io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.0x030x23io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[PORTC:PINC]io_port.bmpAVRSimIOPort.SimIOPortPORTCPort C Data Register0x080x28io_port.bmpNPORTC5Port C Data Register bit 5RW0PORTC4Port C Data Register bit 4RW0PORTC3Port C Data Register bit 3RW0PORTC2Port C Data Register bit 2RW0PORTC1Port C Data Register bit 1RW0PORTC0Port C Data Register bit 0RW0PINCPort C Input PinsThe Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read.0x060x26io_port.bmpNPINC4Port C Input Pins bit 4R0PINC3Port C Input Pins bit 3R0PINC2Port C Input Pins bit 2R0PINC1Port C Input Pins bit 1R0PINC0Port C Input Pins bit 0R0[TCCR0A:TCCR0B:TCNT0H:TCNT0L:OCR0A:OCR0B:TIMSK0:TIFR0:GTCCR]
[TCNT0H:TCNT0L];[OCR0AH:OCR0AL]
io_timer.bmpTCCR0BTimer/Counter0 Control Register B0x250x45io_flag.bmpYCS02Clock Select0 bit 2RW0CS01Clock Select0 bit 1RW0CS00Clock Select0 bit 0RWCLK_SEL_3BIT_EXT0TCCR0ATimer/Counter 0 Control Register A0x240x44io_flag.bmpYTCW0Timer/Counter WidthWhen this bit is written to one 16-bit mode is selected. RW0ICEN0Input Capture Mode EnableThe Input Capture Mode is enabled when this bit is written to one.RW0ICNC0Input Capture Noise CancelerSetting this bit activates the Input Capture Noise Canceler. RW0ICES0Input Capture Edge SelectThis bit selects which edge on the Input Capture Source that is used to trigger a capture event.RW0ICS0Input Capture SelectWhen written logic one, this bit enables the input capture function in Timer/Counter to be triggered by the alternative Input Capture Source.RW0WGM00Waveform Generation ModeThis bit controls the counting sequence of the counterRW0TCNT0HTimer Counter 0 High Byte0x270x47io_timer.bmpNTCNT0H7Timer Counter 0 High Byte bit 7RW0TCNT0H6Timer Counter 0 High Byte bit 6RW0TCNT0H5Timer Counter 0 High Byte bit 5RW0TCNT0H4Timer Counter 0 High Byte bit 4RW0TCNT0H3Timer Counter 0 High Byte bit 3RW0TCNT0H2Timer Counter 0 High Byte bit 2RW0TCNT0H1Timer Counter 0 High Byte bit 1RW0TCNT0H0Timer Counter 0 High Byte bit 0RW0TCNT0LTimer Counter 0 Low Byte0x260x46io_timer.bmpNTCNT0L7Timer Counter 0 Low Byte bit 7RW0TCNT0L6Timer Counter 0 Low Byte bit 6RW0TCNT0L5Timer Counter 0 Low Byte bit 5RW0TCNT0L4Timer Counter 0 Low Byte bit 4RW0TCNT0L3Timer Counter 0 Low Byte bit 3RW0TCNT0L2Timer Counter 0 Low Byte bit 2RW0TCNT0L1Timer Counter 0 Low Byte bit 1RW0TCNT0L0Timer Counter 0 Low Byte bit 0RW0OCR0AOutput Compare Register 0A The Output Compare Register A contains an 8-bit value that is continuously compared with the0x280x48io_timer.bmpNOCR0A7RW0OCR0A6RW0OCR0A5RW0OCR0A4RW0OCR0A3RW0OCR0A2RW0OCR0A1RW0OCR0A0RW0OCR0BOutput Compare Register B 0x290x49io_timer.bmpNOCR0B7RW0OCR0B6RW0OCR0B5RW0OCR0B4RW0OCR0B3RW0OCR0B2RW0OCR0B1RW0OCR0B0RW0TIMSK0Timer/Counter Interrupt Mask RegisterNA0x6Eio_flag.bmpYICIE0Timer/Counter n Input Capture Interrupt EnableRW0OCIE0BTimer/Counter0 Output Compare B Interrupt EnableRW0OCIE0ATimer/Counter0 Output Compare A Interrupt EnableRW0TOIE0Timer/Counter0 Overflow Interrupt EnableRW0TIFR0Timer/Counter Interrupt Flag register0x150x35io_flag.bmpYICF0Timer/Counter 0 Input Capture FlagRW0OCF0BTimer/Counter0 Output Compare Flag BRW0OCF0ATimer/Counter0 Output Compare Flag ARW0TOV0Timer/Counter0 Overflow FlagRW0GTCCRGeneral Timer/Counter Control Register0x230x43io_flag.bmpYTSMTimer/Counter Synchronization ModeRW0PSRSYNCPrescaler ResetRW0[SPMCSR]io_cpu.bmpAVRSimIOSPM.SimIOSPMThe Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write supporSPMCSRStore Program Memory Control and Status RegisterThe Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.0x370x57io_flag.bmpYSPMIESPM Interrupt EnableRW0RWWSBRead-While-Write Section BusyR0SIGRDSignature Row ReadRW0RWWSRERead-While-Write Section Read EnableRW0LBSETLock Bit SetRW0PGWRTPage WriteRW0PGERSPage EraseRW0SPMENStore Program Memory EnableRW0[AVRDragon:AVRISPmkII:STK500_2:JTAGICEmkII:SIMULATOR:STK600:AVRONE:SIMULATOR2]2001002532030x53114510x41128100x400x4C0x000x000x000x414100xC10xC20x000x000x0025625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00100060000151501050x0F25625650x0525625605050x9510DebugWire0x7F,0x01,0xE0,0xF8,0xFF,0x3F,0xB8,0xE00x37,0x01,0x00,0xE0,0xFF,0x1F,0xA8,0xE00X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000x53,0xDB,0x00,0x57,0x33,0x03,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x01,0x17,0x00,0xFF,0x07,0xEF,0x7F0x50,0xDB,0x00,0x50,0x33,0x03,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x00,0x17,0x00,0xCF,0x07,0xEF,0x3F0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x000x570x000x800x040x3F000x3F000x3E000x3C000x38000xFE0x80000x00,320x20,640x000x080x000x000x000x200xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF0xB6,0x01,0x110x3E0x3D0x310x000x000x000x3F000x000x3FAVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt150x280AVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortNAVRSimIOExtInterrupt.SimIOExtInterrupt0x00060x1D0x010x1c0x010x060x010x690x03AVRSimIOExtInterrupt.SimIOExtInterrupt0x00080x1D0x020x1C0x020x060x020x690x0cAVRSimIOExtInterrupt.SimIOExtInterrupt0x000a0x1D0x040x1C0x040x060x040x690x30AVRSimIOExtInterrupt.SimIOExtInterrupt0x000c0x1D0x080x1C0x080x060x080x690xc0AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x00e0x680x010x1b0x010x4c0x000x0fAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x0100x680x020x1b0x020x6c0x030xffAVRSimIOSPM.SimIOSPM0x380xE90xff0xDE0xffAVRSimIOSpi.SimIOSpi0x2c0x030x200x030x800x030x400x030x2e0x10AVRSimADC.SimADC0x2EAvrSimTWI.SimTWI0x02aAvrMasterTimer.MasterTimer12810x0122048:4096:8192:16384:32768:65536:131072:262144:524288:10485762001002532030x53114510x4112860x400x4C0x000x000x000x414100xC10xC20x000x000x0025625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x0010006120050151501050x0F25625650x0525625605050x9510DebugWirelibATmega32HVB.dll