[CORE:INTERRUPT_VECTOR:LOCKBIT:PACKAGE:POWER:PROGVOLT:MEMORY:ADMIN:FUSE:PROGRAMMING:IO_MODULE:ICE_SETTINGS] V3 AVRSimCore32.SimCoreV3 [] [] [] 32 $00 $1B $1A $1D $1C $1F $1E 72 $000 RESET External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. $002 INT0 External Interrupt Request 0 $004 INT1 External Interrupt Request 1 $006 INT2 External Interrupt Request 2 $008 INT3 External Interrupt Request 3 $00A INT4 External Interrupt Request 4 $00C INT5 External Interrupt Request 5 $00E INT6 External Interrupt Request 6 $010 INT7 External Interrupt Request 7 $012 PCINT0 Pin Change Interrupt Request 0 $014 PCINT1 Pin Change Interrupt Request 1 $016 PCINT2 Pin Change Interrupt Request 2 $018 WDT Watchdog Time-out Interrupt $01A TIMER2_COMPA Timer/Counter2 Compare Match A $01C TIMER2_COMPB Timer/Counter2 Compare Match B $01E TIMER2_OVF Timer/Counter2 Overflow $020 TIMER1_CAPT Timer/Counter1 Capture Event $022 TIMER1_COMPA Timer/Counter1 Compare Match A $024 TIMER1_COMPB Timer/Counter1 Compare Match B $026 TIMER1_COMPC Timer/Counter1 Compare Match C $028 TIMER1_OVF Timer/Counter1 Overflow $02A TIMER0_COMPA Timer/Counter0 Compare Match A $02C TIMER0_COMPB Timer/Counter0 Compare Match B $02E TIMER0_OVF Timer/Counter0 Overflow $030 SPI_STC SPI Serial Transfer Complete $032 USART0_RX USART0, Rx Complete $034 USART0_UDRE USART0 Data register Empty $036 USART0_TX USART0, Tx Complete $038 ANALOG_COMP Analog Comparator $03A ADC ADC Conversion Complete $03C EE_READY EEPROM Ready $03E TIMER3_CAPT Timer/Counter3 Capture Event $040 TIMER3_COMPA Timer/Counter3 Compare Match A $042 TIMER3_COMPB Timer/Counter3 Compare Match B $044 TIMER3_COMPC Timer/Counter3 Compare Match C $046 TIMER3_OVF Timer/Counter3 Overflow $048 USART1_RX USART1, Rx Complete $04A USART1_UDRE USART1 Data register Empty $04C USART1_TX USART1, Tx Complete $04E TWI 2-wire Serial Interface $050 SPM_READY Store Program Memory Read $052 TIMER4_CAPT Timer/Counter4 Capture Event $054 TIMER4_COMPA Timer/Counter4 Compare Match A $056 TIMER4_COMPB Timer/Counter4 Compare Match B $058 TIMER4_COMPC Timer/Counter4 Compare Match C $05A TIMER4_OVF Timer/Counter4 Overflow $05C TIMER5_CAPT Timer/Counter5 Capture Event $05E TIMER5_COMPA Timer/Counter5 Compare Match A $060 TIMER5_COMPB Timer/Counter5 Compare Match B $062 TIMER5_COMPC Timer/Counter5 Compare Match C $064 TIMER5_OVF Timer/Counter5 Overflow $066 USART2_RX USART2, Rx Complete $068 USART2_UDRE USART2 Data register Empty $06A USART2_TX USART2, Tx Complete $06C USART3_RX USART3, Rx Complete $06E USART3_UDRE USART3 Data register Empty $070 USART3_TX USART3, Tx Complete $072 TRX24_PLL_LOCK TRX24 - PLL lock interrupt $074 TRX24_PLL_UNLOCK TRX24 - PLL unlock interrupt $076 TRX24_RX_START TRX24 - Receive start interrupt $078 TRX24_RX_END TRX24 - RX_END interrupt $07A TRX24_CCA_ED_DONE TRX24 - CCA/ED done interrupt $07C TRX24_XAH_AMI TRX24 - XAH - AMI $07E TRX24_TX_END TRX24 - TX_END interrupt $080 TRX24_AWAKE TRX24 AWAKE - tranceiver is reaching state TRX_OFF $082 SCNT_CMP1 Symbol counter - compare match 1 interrupt $084 SCNT_CMP2 Symbol counter - compare match 2 interrupt $086 SCNT_CMP3 Symbol counter - compare match 3 interrupt $088 SCNT_OVFL Symbol counter - overflow interrupt $08A SCNT_BACKOFF Symbol counter - backoff interrupt $08C AES_READY AES engine ready interrupt $08E BAT_LOW Battery monitor indicates supply voltage below threshold [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 6 11 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled 0x0C 0x0C Application Protection Mode 1: No lock on SPM and LPM in Application Section 0x0C 0x08 Application Protection Mode 2: SPM prohibited in Application Section 0x0C 0x00 Application Protection Mode 3: LPM and SPM prohibited in Application Section 0x0C 0x04 Application Protection Mode 4: LPM prohibited in Application Section 0x30 0x30 Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section 0x30 0x20 Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section 0x30 0x00 Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section 0x30 0x10 Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section LB1 Lock bit LB2 Lock bit BLB01 Boot Lock bit BLB02 Boot Lock bit BLB11 Boot lock bit BLB12 Boot lock bit [QFN] 64 [PF2:ADC2:DIG2] ADC2, Analog to Digital Converter, Channel 2 : DIG2, Antenna diversity RF switch control (DIG1 inverted) [PF3:ADC3:DIG4] ADC3, Analog to Digital Converter, Channel 3 : DIG4, RX/TX Indicator (DIG3 inverted) [PF4:ADC4:TCK] ADC4, Analog to Digital Converter, channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. [PF5:ADC5:TMS] ADC5, Analog to Digital Converter, channel 5. TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. [PF6:ADC6:TDO] ADC6, Analog to Digital Converter, channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. [PF7:ADC7:TDI] ADC7, Analog to Digital Converter, channel 7. TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. [AVSS_RFP] Ground supply for RF pin RFP. [RFP] RF pin, positive terminal when differential excitation. [RFN] RF pin, negative terminal when differential excitation. [AVSS_RFN] Ground supply for RF pin RFN. [TST] Programming and test mode enable [RSTN] Active low asynchronous reset of the IC [RSTON] Low active reset output pin [PG0:DIG3] DIG3, RX/TX Indicator [PG1:DIG1] DIG1, Antenna diversity RF switch control [PG2:AMR] [PG3:TOSC2] TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the input of the inverting oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin. [PG4:TOSC1] TOSC1, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin. [PG5:OC0B] OC0B, Output Compare and PWM Output B for Timer/Counter 0. [DVSS:DSVSS] Ground & Substrate supply for the digital part of the IC. [DVDD] Digital regulated 1.8V supply voltage [DVDD] Digital regulated 1.8V supply voltage [DEVDD] Digital external supply voltage (IO, voltage regulator) [DVSS] Digital ground supply (core, IO) [PD0:SCL:INT0] INT0, External Interrupt source 0. The PD0 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation [PD1:SDA:INT1] INT1, External Interrupt source 1. The PD1 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation [PD2:RXD1:INT2] INT2, External Interrupt source 2. The PD2 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bi [PD3:TXD1:INT3] INT3, External Interrupt source 3. The PD3 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. [PD4:ICP1] ICP1 - Input Capture Pin1: The PD4 pin can act as an input capture pin for Timer/Counter1. [PD5:XCK1] XCK1, USART1 external clock. The Data Direction Register (DDD4) controls whether the clock is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1 operates in synchronous mode. [PD6:T1] T1, Timer/Counter1 counter source. [PD7:T0] T0, Timer/Counter0 counter source. [CLKI] Input to the internal clock operating circuit of the microcontroller. [DEVDD] Digital external supply voltage (IO) [DVSS] Digital ground supply (IO) [PB0:SSN:PCINT0] SSN: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit. [PB1:SCK:PCINT1] SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. [PB2:MOSI:PDI:PCINT2] MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. PDI, Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line. [PB3:MISO:PDO:PCINT3] MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. PDO, Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line. [PB4:OC2:PCINT4] OC2, Output Compare match output: The PB4 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function. [PB5:OC1A:PCINT5] OC1A, Output Compare matchA output: The PB5 pin can serve as an external output for the Timer/Counter1 output compareA. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. [PB6:OC1B:PCINT6] OC1B, Output Compare matchB output: The PB6 pin can serve as an external output for the Timer/Counter1 output compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. [PB7:OC0A:OC1C:PCINT7] OC2, Output Compare match output: The PB7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function. [DEVDD] Digital external supply voltage (IO) [DVSS] Digital ground supply (IO) [PE0:RXD0:PCINT8] RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up. [PE1:TXD0] TXD0, UART0 Transmit Pin. [PE2:XCK0:AIN0] AIN0 - Analog Comparator Positive Input. This pin is directly connected to the positive input of the analog comparator. XCK0, USART0 external clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in synchronous mode. [PE3:OC3A:AIN1] AIN1 - Analog Comparator Negative Input. This pin is directly connected to the negative input of the analog comparator. OC3A, Output Compare matchA output: The PE3 pin can serve as an external output for the Timer/Counter3 output compareA. The pin has to be configured as an output (DDE3 set (one)) to serve this function. The OC3A pin is also the output pin for the PWM mode timer function. [PE4:OC3B:INT4] INT4, External Interrupt source 4: The PE4 pin can serve as an external interrupt source. OC3B, Output Compare matchB output: The PE4 pin can serve as an external output for the Timer/Counter3 output compareB. The pin has to be configured as an output (DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function. [PE5:OC3C:INT5] INT5, External Interrupt source 5: The PE5 pin can serve as an external interrupt source. OC3C, Output Compare matchC output: The PE5 pin can serve as an external output for the Timer/Counter3 output compareC. The pin has to be configured as an output (DDE5 set (one)) to serve this function. The OC3C pin is also the output pin for the PWM mode timer function. [PE6:T3:INT6] INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source. T3, Timer/Counter3 counter source. [PE7:ICP3:INT7:CLKO] INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. ICP3, Input Capture Pin3: The PE7 pin can act as an input capture pin for Timer/Counter3. CLKO, Clock output: The PE7 pin will be the output of the divided system clock if the CKOUT Fuse is programmed, regardless of the PORTE7 and DDE7 settings. In this case it will be output during reset. [DEVDD] Digital external supply voltage (IO) [DVSS] Digital ground supply (IO) [XTAL2] Output of the inverting 16MHz amplifier. The XTAL2 pin can serve as an external 16MHz reference clock for the transceiver. [XTAL1] Input to the inverting 16MHz oscillator amplifier. [AVSS] Analog ground and substrate supply [EVDD] External supply voltage for the analog part of the IC. [AVDD] Analog regulated 1.8V supply voltage [AVSS:ASVSS] Analog ground and substrate supply [AREF] Analog voltage reference [PF0:ADC0] Analog to Digital Converter, Channel 0 [PF1:ADC1] Analog to Digital Converter, Channel 1 [AVSS] Exposed paddle of the QFN package. 4MHz 25C 5.0mA 2.2mA <3uA 1.8 3.6 1.8 3.6 AVRSimMemory8bit.SimMemory8bit 131072 4096 16384 $200 0 NA $00 $3F $60 $1FF $20 $1FF NA $1FF 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $180 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $17B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $176 0x01 0x02 0x04 0x08 NA $16F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $16E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $16D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $16C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $16B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $16A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $169 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $168 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $167 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA 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0x10 0x20 0x40 0x80 NA $B6 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $B4 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $B3 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $B2 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $B1 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $B0 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $AD 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $AC 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $AB 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $AA 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $A9 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $A8 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $A7 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $A6 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $A5 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $A4 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $A2 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $A1 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $A0 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $9D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $9C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $9B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $9A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $99 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $98 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $97 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $96 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $95 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $94 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $92 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $91 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $90 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $8D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $8C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $8B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $8A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $89 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $88 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $87 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $86 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $85 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $84 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $82 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $81 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $80 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $7F 0x01 0x02 NA $7E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $7D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $7C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $7B 0x40 0x01 0x02 0x04 0x08 0x10 0x20 0x80 NA $7A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $79 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $78 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $77 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $75 0x10 0x20 0x40 NA $73 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $72 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $71 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $70 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $6F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $6E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $6D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $6C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $6B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $6A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $69 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $68 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $67 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $66 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $65 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $64 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $63 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $61 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 NA $60 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3F $5F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3E $5E 0x21 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3D $5D 0xFF 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3C $5C $3B $5B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $37 $57 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $35 $55 0x80 0x01 0x02 0x04 0x08 0x10 $34 $54 0x10 0x01 0x02 0x04 0x08 0x20 0x40 0x80 $33 $53 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $31 $51 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $30 $50 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2E $4E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2D $4D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2C $4C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2B $4B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $2A $4A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $28 $48 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $27 $47 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $26 $46 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $25 $45 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $24 $44 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $23 $43 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $22 $42 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $21 $41 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $20 $40 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1F $3F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1E $3E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1D $3D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1C $3C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1B $3B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1A $3A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $19 $39 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $18 $38 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $17 $37 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $16 $36 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $15 $35 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $14 $34 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $13 $33 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $12 $32 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $11 $31 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $10 $30 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $0F $2F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $0E $2E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $0D $2D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $0C $2C 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $0B $2B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $0A $2A 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $09 $29 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $08 $28 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $07 $27 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $06 $26 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $05 $25 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $04 $24 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $03 $23 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $02 $22 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $01 $21 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $00 $20 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $F000 $FFFF $0000 $EFFF 128 512 4 $0000 $FE00 $FE00 1024 8 $0000 $FC00 $FC00 2048 16 $0000 $F800 $F800 4096 32 $0000 $F000 $F000 ATmega128RFA1 16MHZ 1 RELEASED $1E $A7 $01 3 0x31 0 1 0x00 [LOW:HIGH:EXTENDED] 8 CKDIV8 Divide clock by 8 0 CKOUT Clock output 1 SUT1 Select start-up time 0 SUT0 Select start-up time 0 CKSEL3 Select Clock Source 0 CKSEL2 Select Clock Source 0 CKSEL1 Select Clock Source 1 CKSEL0 Select Clock Source 0 19 0x80 0x00 Divide clock by 8 internally; [CKDIV8=0] 0x40 0x00 Clock output on PORTE7; [CKOUT=0] 0x3F 0x00 Ext. Clock; Start-up time: 6 CK + 0 ms; [SUT=00 CKSEL=0000] 0x3F 0x10 Ext. Clock; Start-up time: 6 CK + 4.1 ms; [SUT=01 CKSEL=0000] 0x3F 0x20 Ext. Clock; Start-up time: 6 CK + 65 ms; [SUT=10 CKSEL=0000] 0x3F 0x02 Int. RC Osc.; Start-up time: 6 CK + 0 ms; [SUT=00 CKSEL=0010] 0x3F 0x12 Int. RC Osc.; Start-up time: 6 CK + 4.1 ms; [SUT=01 CKSEL=0010] 0x3F 0x22 Int. RC Osc.; Start-up time: 6 CK + 65 ms; [SUT=10 CKSEL=0010] 0x3F 0x03 Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms; [SUT=00 CKSEL=0011] 0x3F 0x13 Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms; [SUT=01 CKSEL=0011] 0x3F 0x23 Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms; [SUT=10 CKSEL=0011] 0x3F 0x06 Tranceiver Oscillator; Start-up time: 258 CK + 4.1 ms; [SUT=00 CKSEL=0110] 0x3F 0x16 Tranceiver Oscillator; Start-up time: 258 CK + 65 ms; [SUT=01 CKSEL=0110] 0x3F 0x26 Tranceiver Oscillator; Start-up time: 1K CK + 0 ms; [SUT=10 CKSEL=0110] 0x3F 0x36 Tranceiver Oscillator; Start-up time: 1K CK + 4.1 ms; [SUT=11 CKSEL=0110] 0x3F 0x07 Tranceiver Oscillator; Start-up time: 1K CK + 65 ms; [SUT=00 CKSEL=0111] 0x3F 0x17 Tranceiver Oscillator; Start-up time: 16K CK + 0 ms; [SUT=01 CKSEL=0111] 0x3F 0x27 Tranceiver Oscillator; Start-up time: 16K CK + 4.1 ms; [SUT=10 CKSEL=0111] 0x3F 0x37 Tranceiver Oscillator; Start-up time: 16K CK + 65 ms; [SUT=11 CKSEL=0111] 0x3F 0x08 Tranceiver Oscillator; Start-up time: 258 CK + 4.1 ms; [SUT=00 CKSEL=1000] 0x3F 0x18 Tranceiver Oscillator; Start-up time: 258 CK + 65 ms; [SUT=01 CKSEL=1000] 0x3F 0x28 Tranceiver Oscillator; Start-up time: 1K CK + 0 ms; [SUT=10 CKSEL=1000] 0x3F 0x38 Tranceiver Oscillator; Start-up time: 1K CK + 4.1 ms; [SUT=11 CKSEL=1000] 0x3F 0x09 Tranceiver Oscillator; Start-up time: 1K CK + 65 ms; [SUT=00 CKSEL=1001] 0x3F 0x19 Tranceiver Oscillator; Start-up time: 16K CK + 0 ms; [SUT=01 CKSEL=1001] 0x3F 0x29 Tranceiver Oscillator; Start-up time: 16K CK + 4.1 ms; [SUT=10 CKSEL=1001] 0x3F 0x39 Tranceiver Oscillator; Start-up time: 16K CK + 65 ms; [SUT=11 CKSEL=1001] 0x3F 0x0A Tranceiver Oscillator; Start-up time: 258 CK + 4.1 ms; [SUT=00 CKSEL=1010] 0x3F 0x1A Tranceiver Oscillator; Start-up time: 258 CK + 65 ms; [SUT=01 CKSEL=1010] 0x3F 0x2A Tranceiver Oscillator; Start-up time: 1K CK + 0 ms; [SUT=10 CKSEL=1010] 0x3F 0x3A Tranceiver Oscillator; Start-up time: 1K CK + 4.1 ms; [SUT=11 CKSEL=1010] 0x3F 0x0B Tranceiver Oscillator; Start-up time: 1K CK + 65 ms; [SUT=00 CKSEL=1011] 0x3F 0x1B Tranceiver Oscillator; Start-up time: 16K CK + 0 ms; [SUT=01 CKSEL=1011] 0x3F 0x2B Tranceiver Oscillator; Start-up time: 16K CK + 4.1 ms; [SUT=10 CKSEL=1011] 0x3F 0x3B Tranceiver Oscillator; Start-up time: 16K CK + 65 ms; [SUT=11 CKSEL=1011] 0x3F 0x0C Tranceiver Oscillator; Start-up time: 258 CK + 4.1 ms; [SUT=00 CKSEL=1100] 0x3F 0x1C Tranceiver Oscillator; Start-up time: 258 CK + 65 ms; [SUT=01 CKSEL=1100] 0x3F 0x2C Tranceiver Oscillator; Start-up time: 1K CK + 0 ms; [SUT=10 CKSEL=1100] 0x3F 0x3C Tranceiver Oscillator; Start-up time: 1K CK + 4.1 ms; [SUT=11 CKSEL=1100] 0x3F 0x0D Tranceiver Oscillator; Start-up time: 1K CK + 65 ms; [SUT=00 CKSEL=1101] 0x3F 0x1D Tranceiver Oscillator; Start-up time: 16K CK + 0 ms; [SUT=01 CKSEL=1101] 0x3F 0x2D Tranceiver Oscillator; Start-up time: 16K CK + 4.1 ms; [SUT=10 CKSEL=1101] 0x3F 0x3D Tranceiver Oscillator; Start-up time: 16K CK + 65 ms; [SUT=11 CKSEL=1101] 0x3F 0x0E Tranceiver Oscillator; Start-up time: 258 CK + 4.1 ms; [SUT=00 CKSEL=1110] 0x3F 0x1E Tranceiver Oscillator; Start-up time: 258 CK + 65 ms; [SUT=01 CKSEL=1110] 0x3F 0x2E Tranceiver Oscillator; Start-up time: 1K CK + 0 ms; [SUT=10 CKSEL=1110] 0x3F 0x3E Tranceiver Oscillator; Start-up time: 1K CK + 4.1 ms; [SUT=11 CKSEL=1110] 0x3F 0x0F Tranceiver Oscillator; Start-up time: 1K CK + 65 ms; [SUT=00 CKSEL=1111] 0x3F 0x1F Tranceiver Oscillator; Start-up time: 16K CK + 0 ms; [SUT=01 CKSEL=1111] 0x3F 0x2F Tranceiver Oscillator; Start-up time: 16K CK + 4.1 ms; [SUT=10 CKSEL=1111] 0x3F 0x3F Tranceiver Oscillator; Start-up time: 16K CK + 65 ms; [SUT=11 CKSEL=1111] 8 OCDEN Enable OCD 1 JTAGEN Enable JTAG 0 SPIEN Enable Serial programming and Data Downloading 0 WDTON Watchdog timer always on 1 EESAVE EEPROM memory is preserved through chip erase 1 BOOTSZ1 Select Boot Size 0 BOOTSZ0 Select Boot Size 0 BOOTRST Select Reset Vector 1 10 0x80 0x00 On-Chip Debug Enabled; [OCDEN=0] 0x40 0x00 JTAG Interface Enabled; [JTAGEN=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x10 0x00 Watchdog timer always on; [WDTON=0] 0x08 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x06 0x06 Boot Flash section size=512 words Boot start address=$FE00; [BOOTSZ=11] 0x06 0x04 Boot Flash section size=1024 words Boot start address=$FC00; [BOOTSZ=10] 0x06 0x02 Boot Flash section size=2048 words Boot start address=$F800; [BOOTSZ=01] 0x06 0x00 Boot Flash section size=4096 words Boot start address=$F000; [BOOTSZ=00] ; default value 0x01 0x00 Boot Reset vector Enabled (default address=$0000); [BOOTRST=0] 3 BODLEVEL2 Brown-out Detector trigger level 1 BODLEVEL1 Brown-out Detector trigger level 1 BODLEVEL0 Brown-out Detector trigger level 1 4 0x07 0x07 Brown-out detection disabled; [BODLEVEL=111] 0x07 0x06 Brown-out detection level at VCC=1.8 V; [BODLEVEL=110] 0x07 0x05 Brown-out detection level at VCC=1.9 V; [BODLEVEL=101] 0x07 0x04 Brown-out detection level at VCC=2.0 V; [BODLEVEL=100] 0x07 0x03 Brown-out detection level at VCC=2.1 V; [BODLEVEL=011] 0x07 0x02 Brown-out detection level at VCC=2.2 V; [BODLEVEL=010] 0x07 0x01 Brown-out detection level at VCC=2.3 V; [BODLEVEL=001] 0x07 0x00 Brown-out detection level at VCC=2.4 V; [BODLEVEL=000] 0xff,0xdf 0xff,0xdf 1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 0x00,8.0 MHz 256 8 [ANALOG_COMPARATOR:USART0:USART1:TWI:SPI:PORTA:PORTB:PORTC:PORTD:PORTE:PORTF:PORTG:TIMER_COUNTER_0:TIMER_COUNTER_2:WATCHDOG:TIMER_COUNTER_5:TIMER_COUNTER_4:TIMER_COUNTER_3:TIMER_COUNTER_1:TRX24:SYMCNT:EEPROM:JTAG:EXTERNAL_INTERRUPT:AD_CONVERTER:BOOT_LOAD:CPU:FLASH:PWRCTRL:USART0_SPI:USART1_SPI] [ADCSRB:ACSR:DIDR1] io_analo.bmp AlgComp_01 ADCSRB ADC Control and Status Register B NA $7B io_flag.bmp Y ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer defines the negative input of the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see section "Analog Comparator Multiplexed Input". RW 0 ACSR Analog Comparator Control And Status Register $30 $50 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage connects to the positive input of the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. When the bandgap reference is used as the input of the Analog Comparator, it will take a certain time for the voltage to stabilize. If not stabilized, the first comparison may give a wrong value. See section "Internal Voltage Reference" for details. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is activated. When written logic zero, the interrupt is disabled. RW 0 ACIC Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. RW 0 ACIS1 Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in the following table. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. RW 0 ACIS0 Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in the following table. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. RW ANALOG_COMP_INTERRUPT 0 DIDR1 Digital Input Disable Register 1 NA $7F io_analo.bmp Y AIN1D AIN1 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 AIN0D AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 [UDR0:UCSR0A:UCSR0B:UCSR0C:UBRR0H:UBRR0L] [UBRR0H:UBRR0L] io_com.bmp The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: Full Duplex Operation (Independent Serial Receive and Transmit Registers), Asynchronous or Synchronous Operation, Master or Slave Clocked Synchronous Operation, High Resolution Baud Rate Generator, supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits, Odd or Even Parity Generation and Parity Check Supported by Hardware, Data OverRun Detection, Framing Error Detection, Noise Filtering includes False Start Bit Detection and Digital Low Pass Filter, three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete, Multi-processor Communication Mode and Double Speed Asynchronous Communication Mode. The ATmega128RFA1 has two USARTs: USART0 and USART1. UDR0 USART0 I/O Data Register The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR0. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR0 Register location. Reading the UDR0 Register location will return the contents of the Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE0 Flag in the UCSR0A Register is set. Data written to UDR0 when the UDRE0 Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxD0 pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. NA $C6 io_com.bmp N UDR07 USART I/O Data Register RW 0 UDR06 USART I/O Data Register RW 0 UDR05 USART I/O Data Register RW 0 UDR04 USART I/O Data Register RW 0 UDR03 USART I/O Data Register RW 0 UDR02 USART I/O Data Register RW 0 UDR01 USART I/O Data Register RW 0 UDR00 USART I/O Data Register RW 0 USART_DATA_REG_BITF UCSR0A USART0 Control and Status Register A NA $C0 io_flag.bmp Y RXC0 USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXC0 bit will become zero. The RXC0 Flag can be used to generate a Receive Complete interrupt (see description of the RXCIE0 bit). R 0 TXC0 USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR0). The TXC0 Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC0 Flag can generate a Transmit Complete interrupt (see description of the TXCIE0 bit). RW 0 UDRE0 USART Data Register Empty The UDRE0 Flag indicates if the transmit buffer (UDR0) is ready to receive new data. If UDRE0 is one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag can generate a Data Register Empty interrupt (see description of the UDRIE0 bit). UDRE0 is set after a reset to indicate that the Transmitter is ready. R 1 FE0 Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDR0) is read. The FE0 bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSR0A. R 0 DOR0 Data OverRun This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register and a new start bit is detected. This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A. R 0 UPE0 USART Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM01 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A. R 0 U2X0 Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. RW 0 MPCM0 Multi-processor Communication Mode This bit enables the Multi-processor Communication mode. When the MPCM0 bit is written to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM0 setting. For more detailed information see section "Multi-processor Communication Mode". RW 0 UCSR0B USART0 Control and Status Register B NA $C1 io_flag.bmp Y RXCIE0 RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC0 Flag. A USART Receive Complete interrupt will be generated only if the RXCIE0 bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC0 bit in UCSR0A is set. RW 0 TXCIE0 TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC0 Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE0 bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC0 bit in UCSR0A is set. RW 0 UDRIE0 USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Empty interrupt will be generated only if the UDRIE0 bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE0 bit in UCSR0A is set. RW 1 RXEN0 Receiver Enable Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxD0 pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FE0, DOR0 and UPE0 Flags. RW 0 TXEN0 Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD0 pin when enabled. The disabling of the Transmitter (writing TXEN0 to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD0 port. RW 0 UCSZ02 Character Size The UCSZ02 bits combined with the UCSZ01:0 bit in UCSR0C sets the number of data bits (Character Size) in the frame that the Receiver and Transmitter use. RW 0 RXB80 Receive Data Bit 8 RXB80 is the 9th data bit of the received character when operating with serial frames with nine data bits. The bit must be read before reading the lower 8 bits from UDR0. R 0 TXB80 Transmit Data Bit 8 TXB80 is the 9th data bit in the character to be transmitted when operating with serial frames with nine data bits. The bit must be written before writing the lower 8 bits to UDR0. W 0 UCSR0C USART0 Control and Status Register C NA $C2 io_flag.bmp Y UMSEL01 UMSEL1 USART Mode Select These bits select the mode of operation of the USART0 as shown in the following table. See section "USART in SPI Mode" for a full description of the Master SPI Mode (MSPIM) operation. RW 0 UMSEL00 UMSEL0 USART Mode Select These bits select the mode of operation of the USART0 as shown in the following table. See section "USART in SPI Mode" for a full description of the Master SPI Mode (MSPIM) operation. RW COMM_USART_MODE_2BIT_MEGARF 0 UPM01 Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the UPE0 Flag in UCSR0A will be set. RW 0 UPM00 Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the UPE0 Flag in UCSR0A will be set. RW COMM_UPM_PARITY_MODE 0 USBS0 Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. RW COMM_STOP_BIT_SEL 0 UCSZ01 UDORD0 Character Size The UCSZ01:0 bits combined with the UCSZ02 bit in UCSR0B sets the number of data bits (Character Size) in the frame that the Receiver and Transmitter use. RW 0 UCSZ00 UCPHA0 Character Size The UCSZ01:0 bits combined with the UCSZ02 bit in UCSR0B sets the number of data bits (Character Size) in the frame that the Receiver and Transmitter use. RW 1 USART_CHAR_SIZE_BITF UCPOL0 Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL0 bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK0). RW 0 USART_CLK_POLARITY_BITF UBRR0H USART0 Baud Rate Register High Byte UBRR0 is a 12-bit register which contains the USART baud rate. The UBRR0H contains the four most significant bits, and the UBRR0L contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. NA $C5 io_com.bmp N Res3 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 UBRR11 USART Baud Rate Register These bits represent bits [11:8] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR10 USART Baud Rate Register These bits represent bits [11:8] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR9 USART Baud Rate Register These bits represent bits [11:8] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR8 USART Baud Rate Register These bits represent bits [11:8] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 USART_BAUD_RATE_HB_BITF UBRR0L USART0 Baud Rate Register Low Byte UBRR0 is a 12-bit register which contains the USART baud rate. The UBRR0H contains the four most significant bits, and the UBRR0L contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. NA $C4 io_com.bmp N UBRR7 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR6 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR5 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR4 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR3 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR2 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR1 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR0 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 USART_BAUD_RATE_LB_BITF [UDR1:UCSR1A:UCSR1B:UCSR1C:UBRR1H:UBRR1L] [UBRR1H:UBRR1L] io_com.bmp The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: Full Duplex Operation (Independent Serial Receive and Transmit Registers), Asynchronous or Synchronous Operation, Master or Slave Clocked Synchronous Operation, High Resolution Baud Rate Generator, supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits, Odd or Even Parity Generation and Parity Check Supported by Hardware, Data OverRun Detection, Framing Error Detection, Noise Filtering includes False Start Bit Detection and Digital Low Pass Filter, three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete, Multi-processor Communication Mode and Double Speed Asynchronous Communication Mode. The ATmega128RFA1 has two USARTs: USART0 and USART1. UDR1 USART1 I/O Data Register The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR1. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR1 Register location. Reading the UDR1 Register location will return the contents of the Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE1 Flag in the UCSR1A Register is set. Data written to UDR1 when the UDRE1 Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxD1 pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. NA $CE io_com.bmp N UDR17 USART I/O Data Register RW 0 UDR16 USART I/O Data Register RW 0 UDR15 USART I/O Data Register RW 0 UDR14 USART I/O Data Register RW 0 UDR13 USART I/O Data Register RW 0 UDR12 USART I/O Data Register RW 0 UDR11 USART I/O Data Register RW 0 UDR10 USART I/O Data Register RW 0 USART_DATA_REG_BITF UCSR1A USART1 Control and Status Register A NA $C8 io_flag.bmp Y RXC1 USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXC1 bit will become zero. The RXC1 Flag can be used to generate a Receive Complete interrupt (see description of the RXCIE1 bit). R 0 TXC1 USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR1). The TXC1 Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC1 Flag can generate a Transmit Complete interrupt (see description of the TXCIE1 bit). RW 0 UDRE1 USART Data Register Empty The UDRE1 Flag indicates if the transmit buffer (UDR1) is ready to receive new data. If UDRE1 is one, the buffer is empty, and therefore ready to be written. The UDRE1 Flag can generate a Data Register Empty interrupt (see description of the UDRIE1 bit). UDRE1 is set after a reset to indicate that the Transmitter is ready. R 1 FE1 Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDR1) is read. The FE1 bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSR1A. R 0 DOR1 Data OverRun This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register and a new start bit is detected. This bit is valid until the receive buffer (UDR1) is read. Always set this bit to zero when writing to UCSR1A. R 0 UPE1 USART Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM11 = 1). This bit is valid until the receive buffer (UDR1) is read. Always set this bit to zero when writing to UCSR1A. R 0 U2X1 Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. RW 0 MPCM1 Multi-processor Communication Mode This bit enables the Multi-processor Communication mode. When the MPCM1 bit is written to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM1 setting. For more detailed information see section "Multi-processor Communication Mode". RW 0 UCSR1B USART1 Control and Status Register B NA $C9 io_flag.bmp Y RXCIE1 RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC1 Flag. A USART Receive Complete interrupt will be generated only if the RXCIE1 bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC1 bit in UCSR1A is set. RW 0 TXCIE1 TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC1 Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE1 bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC1 bit in UCSR1A is set. RW 0 UDRIE1 USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE1 Flag. A Data Register Empty interrupt will be generated only if the UDRIE1 bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE1 bit in UCSR1A is set. RW 1 RXEN1 Receiver Enable Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxD1 pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FE1, DOR1 and UPE1 Flags. RW 0 TXEN1 Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD1 pin when enabled. The disabling of the Transmitter (writing TXEN1 to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD1 port. RW 0 UCSZ12 Character Size The UCSZ12 bits combined with the UCSZ11:0 bit in UCSR1C sets the number of data bits (Character Size) in the frame that the Receiver and Transmitter use. RW 0 RXB81 Receive Data Bit 8 RXB81 is the 9th data bit of the received character when operating with serial frames with nine data bits. The bit must be read before reading the lower 8 bits from UDR1. R 0 TXB81 Transmit Data Bit 8 TXB81 is the 9th data bit in the character to be transmitted when operating with serial frames with nine data bits. The bit must be written before writing the lower 8 bits to UDR1. W 0 UCSR1C USART1 Control and Status Register C NA $CA io_flag.bmp Y UMSEL11 USART Mode Select These bits select the mode of operation of the USART1 as shown in the following table. See section "USART in SPI Mode" for a full description of the Master SPI Mode (MSPIM) operation. RW 0 UMSEL10 USART Mode Select These bits select the mode of operation of the USART1 as shown in the following table. See section "USART in SPI Mode" for a full description of the Master SPI Mode (MSPIM) operation. RW COMM_USART_MODE_2BIT_MEGARF 0 UPM11 Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM1 setting. If a mismatch is detected, the UPE1 Flag in UCSR1A will be set. RW 0 UPM10 Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM1 setting. If a mismatch is detected, the UPE1 Flag in UCSR1A will be set. RW COMM_UPM_PARITY_MODE 0 USBS1 Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. RW COMM_STOP_BIT_SEL 0 UCSZ11 UDORD1 Character Size The UCSZ11:0 bits combined with the UCSZ12 bit in UCSR1B sets the number of data bits (Character Size) in the frame that the Receiver and Transmitter use. RW 1 UCSZ10 UCPHA1 Character Size The UCSZ11:0 bits combined with the UCSZ12 bit in UCSR1B sets the number of data bits (Character Size) in the frame that the Receiver and Transmitter use. RW 1 USART_CHAR_SIZE_BITF UCPOL1 Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL1 bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK1). RW 0 USART_CLK_POLARITY_BITF UBRR1H USART1 Baud Rate Register High Byte UBRR1 is a 12-bit register which contains the USART baud rate. The UBRR1H contains the four most significant bits, and the UBRR1L contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRR1L will trigger an immediate update of the baud rate prescaler. NA $CD io_com.bmp N Res3 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 UBRR11 USART Baud Rate Register These bits represent bits [11:8] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR10 USART Baud Rate Register These bits represent bits [11:8] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR9 USART Baud Rate Register These bits represent bits [11:8] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR8 USART Baud Rate Register These bits represent bits [11:8] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 USART_BAUD_RATE_HB_BITF UBRR1L USART1 Baud Rate Register Low Byte UBRR1 is a 12-bit register which contains the USART baud rate. The UBRR1H contains the four most significant bits, and the UBRR1L contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRR1L will trigger an immediate update of the baud rate prescaler. NA $CC io_com.bmp N UBRR7 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR6 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR5 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR4 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR3 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR2 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR1 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 UBRR0 USART Baud Rate Register These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". RW 0 USART_BAUD_RATE_LB_BITF [TWAMR:TWBR:TWCR:TWSR:TWDR:TWAR] io_com.bmp The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Features: Simple yet powerful and flexible communication interface, only two bus lines needed; Both master and slave operation supported; Device can operate as transmitter or receiver; 7-bit address space allows up to 128 different slave addresses; Multi-master arbitration support; Up to 400 kHz data transfer speed; Slew-rate limited output drivers; Noise suppression circuitry rejects spikes on bus lines; Fully programmable slave address with general call support; Address recognition causes wake-up when AVR is in sleep mode. TWAMR TWI (Slave) Address Mask Register NA $BD io_com.bmp Y TWAM6 TWAMR6 TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. RW 0 TWAM5 TWAMR5 TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. RW 0 TWAM4 TWAMR4 TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. RW 0 TWAM3 TWAMR3 TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. RW 0 TWAM2 TWAMR2 TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. RW 0 TWAM1 TWAMR1 TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. RW 0 TWAM0 TWAMR0 TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 TWBR TWI Bit Rate Register The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. NA $B8 io_com.bmp N TWBR7 TWI Bit Rate Register Value The TWBR register selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See section "Bit Rate Generator Unit" for calculating bit rates. RW 0 TWBR6 TWI Bit Rate Register Value The TWBR register selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See section "Bit Rate Generator Unit" for calculating bit rates. RW 0 TWBR5 TWI Bit Rate Register Value The TWBR register selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See section "Bit Rate Generator Unit" for calculating bit rates. RW 0 TWBR4 TWI Bit Rate Register Value The TWBR register selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See section "Bit Rate Generator Unit" for calculating bit rates. RW 0 TWBR3 TWI Bit Rate Register Value The TWBR register selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See section "Bit Rate Generator Unit" for calculating bit rates. RW 0 TWBR2 TWI Bit Rate Register Value The TWBR register selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See section "Bit Rate Generator Unit" for calculating bit rates. RW 0 TWBR1 TWI Bit Rate Register Value The TWBR register selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See section "Bit Rate Generator Unit" for calculating bit rates. RW 0 TWI_BIT_RATE_BITF TWBR0 TWI Bit Rate Register Value The TWBR register selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See section "Bit Rate Generator Unit" for calculating bit rates. RW 0 TWCR TWI Control Register The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are put into the TWDR. It also indicates a write collision if data writing to TWDR is attempted while the register is inaccessible. NA $BC io_flag.bmp Y TWINT TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI. So all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR) and TWI Data Register (TWDR) must be complete before clearing this flag. RW 0 TWEA TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1. The devices own slave address has been received; 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. RW 0 TWSTA TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire Serial Bus. The TWI hardware checks if the bus is available and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. RW 0 TWSTO TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined not-addressed Slave mode and releases the SCL and SDA lines to a high impedance state. RW 0 TWWC TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high. RW 0 TWEN TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O ports connected to the SCL and SDA pins enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated regardless of any ongoing operation. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 TWIE TWI Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high. RW 0 TWSR TWI Status Register NA $B9 io_flag.bmp Y TWS7 TWI Status These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes for both transmitter and receiver mode are described in the following table. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. RW 0 TWS6 TWI Status These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes for both transmitter and receiver mode are described in the following table. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. RW 0 TWS5 TWI Status These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes for both transmitter and receiver mode are described in the following table. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. RW 0 TWS4 TWI Status These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes for both transmitter and receiver mode are described in the following table. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. RW 0 TWS3 TWI Status These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes for both transmitter and receiver mode are described in the following table. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. RW 0 TWI_STATUS_BITF Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 TWPS1 TWI Prescaler Bits These bits can be read and written and control the bit rate of the prescaler. RW 0 TWPS0 TWI Prescaler Bits These bits can be read and written and control the bit rate of the prescaler. RW COMM_TWI_PRESACLE 0 TWDR TWI Data Register In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is automatically controlled by the TWI logic. The CPU cannot access the ACK bit directly. NA $BB io_com.bmp N TWD7 TWI Data Register Byte RW 1 TWD6 TWI Data Register Byte RW 1 TWD5 TWI Data Register Byte RW 1 TWD4 TWI Data Register Byte RW 1 TWD3 TWI Data Register Byte RW 1 TWD2 TWI Data Register Byte RW 1 TWD1 TWI Data Register Byte RW 1 TWD0 TWI Data Register Byte RW 1 TWI_DATA_REGISTER_BITF TWAR TWI (Slave) Address Register The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver. This register is not needed in the Master modes. In multi-master systems TWAR must be set in Masters which can be addressed as Slaves by other Masters. The LSB of TWAR is used to enable the recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. NA $BA io_com.bmp Y TWA6 TWI (Slave) Address These bits contain the TWI address operated as a Slave device. RW 0 TWA5 TWI (Slave) Address These bits contain the TWI address operated as a Slave device. RW 0 TWA4 TWI (Slave) Address These bits contain the TWI address operated as a Slave device. RW 0 TWA3 TWI (Slave) Address These bits contain the TWI address operated as a Slave device. RW 0 TWA2 TWI (Slave) Address These bits contain the TWI address operated as a Slave device. RW 0 TWA1 TWI (Slave) Address These bits contain the TWI address operated as a Slave device. RW 0 TWA0 TWI (Slave) Address These bits contain the TWI address operated as a Slave device. RW 0 TWGCE TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus. RW 0 [SPDR:SPSR:SPCR] io_com.bmp The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega128RFA1 and peripheral devices or between several AVR devices. The SPI modules includes the following features: Full-duplex, Three-wire Synchronous Data Transfer; Master or Slave Operation; LSB First or MSB First Data Transfer; Seven Programmable Bit Rates; End of Transmission Interrupt Flag; Write Collision Flag Protection; Wake-up from Idle Mode; Double Speed (CK/2) Master SPI Mode. The USART can also be used in Master SPI mode. The Power Reduction SPI bit PRSPI in PRR0 must be written to zero to enable SPI module. SPCR SPI Control Register $2C $4C io_flag.bmp Y SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.s RW 0 SPE SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. RW 0 DORD Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. RW 0 MSTR Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If the Slave Select pin is configured as an input and is driven low while MSTR is set, MSTR will be cleared and SPIF in SPSR are set. The user will then have to set MSTR to re-enable SPI Master mode. RW 0 CPOL Clock polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to the "Data Modes" section for an example. The CPOL functionality is summarized below. RW 0 SPI_CPOL_BITF CPHA Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to the "Data Modes" section for an example. The CPOL functionality is summarized below. RW 0 SPI_CPHA_BITF SPR1 SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table. RW 0 SPR0 SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table. RW COMM_SCK_RATE_3BIT 0 SPSR SPI Status Register $2D $4D io_flag.bmp Y SPIF SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. The SPIF Flag is also set if the Slave Select pin is an input and is driven low when the SPI is in Master mode. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set and then accessing the SPI Data Register (SPDR). R 0 WCOL Write Collision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set and then accessing the SPI Data Register. R 0 Res4 Reserved R 0 Res3 Reserved R 0 Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode. This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower. The SPI interface on the ATmega128RFA1 is also used for program memory and EEPROM downloading or uploading. See section "Serial Downloading" for serial programming and verification. RW 0 SPDR SPI Data Register The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. $2E $4E io_com.bmp N SPDR7 SPI Data Register RW X SPDR6 SPI Data Register RW X SPDR5 SPI Data Register RW X SPDR4 SPI Data Register RW X SPDR3 SPI Data Register RW X SPDR2 SPI Data Register RW X SPDR1 SPI Data Register R 0 SPDR0 SPI Data Register R SPI_DATA_REG_BITF 0 [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register The PORTA register can be used as a General Purpose I/O Register for storing any information. $02 $22 io_port.bmp N PORTA7 Port A Data Register Value RW 0 PORTA6 Port A Data Register Value RW 0 PORTA5 Port A Data Register Value RW 0 PORTA4 Port A Data Register Value RW 0 PORTA3 Port A Data Register Value RW 0 PORTA2 Port A Data Register Value RW 0 PORTA1 Port A Data Register Value RW 0 PORTA0 Port A Data Register Value RW 0 DDRA Port A Data Direction Register The DDRA register can be used as a General Purpose I/O Register for storing any information. $01 $21 io_flag.bmp N DDA7 Port A Data Direction Register Value RW 0 DDA6 Port A Data Direction Register Value RW 0 DDA5 Port A Data Direction Register Value RW 0 DDA4 Port A Data Direction Register Value RW 0 DDA3 Port A Data Direction Register Value RW 0 DDA2 Port A Data Direction Register Value RW 0 DDA1 Port A Data Direction Register Value RW 0 DDA0 Port A Data Direction Register Value RW 0 PINA Port A Input Pins Address The PINA register is reserved for interal use and cannot be used as a General Purpose I/O Register. $00 $20 io_port.bmp N PINA7 Port A Input Pins RW 0 PINA6 Port A Input Pins RW 0 PINA5 Port A Input Pins RW 0 PINA4 Port A Input Pins RW 0 PINA3 Port A Input Pins RW 0 PINA2 Port A Input Pins RW 0 PINA1 Port A Input Pins RW 0 PINA0 Port A Input Pins RW 0 [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register If PORTBn is written logic one when the PORTB pin n is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTBn has to be written logic zero or the pin has to be configured as an output pin. If PORTBn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTBn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). $05 $25 io_port.bmp N PORTB7 Port B Data Register Value RW 0 PORTB6 Port B Data Register Value RW 0 PORTB5 Port B Data Register Value RW 0 PORTB4 Port B Data Register Value RW 0 PORTB3 Port B Data Register Value RW 0 PORTB2 Port B Data Register Value RW 0 PORTB1 Port B Data Register Value RW 0 PORTB0 Port B Data Register Value RW 0 PORT_DATA_REG_BITF DDRB Port B Data Direction Register The DDBn bit in the DDRB Register selects the direction of the PORTB pin n. If DDBn is written logic one, PBn is configured as an output pin. If DDBn is written logic zero, PBn is configured as an input pin. $04 $24 io_flag.bmp N DDB7 Port B Data Direction Register Value RW 0 DDB6 Port B Data Direction Register Value RW 0 DDB5 Port B Data Direction Register Value RW 0 DDB4 Port B Data Direction Register Value RW 0 DDB3 Port B Data Direction Register Value RW 0 DDB2 Port B Data Direction Register Value RW 0 DDB1 Port B Data Direction Register Value RW 0 DDB0 Port B Data Direction Register Value RW 0 DDR_VALUE_BITF PINB Port B Input Pins Address This register allows access to the PORTB pins independent of the setting of the Data Direction bit DDBn. The port pin can be read through the PINBn Register bit, and writing a logic one to PINBn toggles the value of PORTBn. $03 $23 io_port.bmp N PINB7 Port B Input Pins Value R 0 PINB6 Port B Input Pins Value R 0 PINB5 Port B Input Pins Value R 0 PINB4 Port B Input Pins Value R 0 PINB3 Port B Input Pins Value R 0 PINB2 Port B Input Pins Value R 0 PINB1 Port B Input Pins Value R 0 PINB0 Port B Input Pins Value R 0 PIN_VALUE_BITF [PORTC:DDRC:PINC] io_port.bmp AVRSimIOPort.SimIOPort PORTC Port C Data Register The PORTC register can be used as a General Purpose I/O Register for storing any information. $08 $28 io_port.bmp N PORTC7 Port C Data Register Value RW 0 PORTC6 Port C Data Register Value RW 0 PORTC5 Port C Data Register Value RW 0 PORTC4 Port C Data Register Value RW 0 PORTC3 Port C Data Register Value RW 0 PORTC2 Port C Data Register Value RW 0 PORTC1 Port C Data Register Value RW 0 PORTC0 Port C Data Register Value RW 0 DDRC Port C Data Direction Register The DDRC register can be used as a General Purpose I/O Register for storing any information. $07 $27 io_flag.bmp N DDC7 Port C Data Direction Register Value RW 0 DDC6 Port C Data Direction Register Value RW 0 DDC5 Port C Data Direction Register Value RW 0 DDC4 Port C Data Direction Register Value RW 0 DDC3 Port C Data Direction Register Value RW 0 DDC2 Port C Data Direction Register Value RW 0 DDC1 Port C Data Direction Register Value RW 0 DDC0 Port C Data Direction Register Value RW 0 PINC Port C Input Pins Address The PINC register is reserved for interal use and cannot be used as a General Purpose I/O Register. $06 $26 io_port.bmp N PINC7 Port C Input Pins R 0 PINC6 Port C Input Pins R 0 PINC5 Port C Input Pins R 0 PINC4 Port C Input Pins R 0 PINC3 Port C Input Pins R 0 PINC2 Port C Input Pins R 0 PINC1 Port C Input Pins R 0 PINC0 Port C Input Pins R 0 [PORTD:DDRD:PIND] io_port.bmp AVRSimIOPort.SimIOPort PORTD Port D Data Register If PORTDn is written logic one when the PORTD pin n is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTDn has to be written logic zero or the pin has to be configured as an output pin. If PORTDn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTDn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). $0B $2B io_port.bmp N PORTD7 Port D Data Register Value RW 0 PORTD6 Port D Data Register Value RW 0 PORTD5 Port D Data Register Value RW 0 PORTD4 Port D Data Register Value RW 0 PORTD3 Port D Data Register Value RW 0 PORTD2 Port D Data Register Value RW 0 PORTD1 Port D Data Register Value RW 0 PORTD0 Port D Data Register Value RW 0 PORT_DATA_REG_BITF DDRD Port D Data Direction Register The DDDn bit in the DDRD Register selects the direction of the PORTD pin n. If DDDn is written logic one, PDn is configured as an output pin. If DDDn is written logic zero, PDn is configured as an input pin. $0A $2A io_flag.bmp N DDD7 Port D Data Direction Register Value RW 0 DDD6 Port D Data Direction Register Value RW 0 DDD5 Port D Data Direction Register Value RW 0 DDD4 Port D Data Direction Register Value RW 0 DDD3 Port D Data Direction Register Value RW 0 DDD2 Port D Data Direction Register Value RW 0 DDD1 Port D Data Direction Register Value RW 0 DDD0 Port D Data Direction Register Value RW 0 DDR_VALUE_BITF PIND Port D Input Pins Address This register allows access to the PORTD pins independent of the setting of the Data Direction bit DDDn. The port pin can be read through the PINDn Register bit, and writing a logic one to PINDn toggles the value of PORTDn. $09 $29 io_port.bmp N PIND7 Port D Input Pins Value R 0 PIND6 Port D Input Pins Value R 0 PIND5 Port D Input Pins Value R 0 PIND4 Port D Input Pins Value R 0 PIND3 Port D Input Pins Value R 0 PIND2 Port D Input Pins Value R 0 PIND1 Port D Input Pins Value R 0 PIND0 Port D Input Pins Value R 0 PIN_VALUE_BITF [PORTE:DDRE:PINE] io_port.bmp AVRSimIOPort.SimIOPort PORTE Port E Data Register If PORTEn is written logic one when the PORTE pin n is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTEn has to be written logic zero or the pin has to be configured as an output pin. If PORTEn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTEn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). $0E $2E io_port.bmp N PORTE7 Port E Data Register Value RW 0 PORTE6 Port E Data Register Value RW 0 PORTE5 Port E Data Register Value RW 0 PORTE4 Port E Data Register Value RW 0 PORTE3 Port E Data Register Value RW 0 PORTE2 Port E Data Register Value RW 0 PORTE1 Port E Data Register Value RW 0 PORTE0 Port E Data Register Value RW 0 PORT_DATA_REG_BITF DDRE Port E Data Direction Register The DDEn bit in the DDRE Register selects the direction of the PORTE pin n. If DDEn is written logic one, PEn is configured as an output pin. If DDEn is written logic zero, PEn is configured as an input pin. $0D $2D io_flag.bmp N DDE7 Port E Data Direction Register Value RW 0 DDE6 Port E Data Direction Register Value RW 0 DDE5 Port E Data Direction Register Value RW 0 DDE4 Port E Data Direction Register Value RW 0 DDE3 Port E Data Direction Register Value RW 0 DDE2 Port E Data Direction Register Value RW 0 DDE1 Port E Data Direction Register Value RW 0 DDE0 Port E Data Direction Register Value RW 0 DDR_VALUE_BITF PINE Port E Input Pins Address This register allows access to the PORTE pins independent of the setting of the Data Direction bit DDEn. The port pin can be read through the PINEn Register bit, and writing a logic one to PINEn toggles the value of PORTEn. $0C $2C io_port.bmp N PINE7 Port E Input Pins Value R 0 PINE6 Port E Input Pins Value R 0 PINE5 Port E Input Pins Value R 0 PINE4 Port E Input Pins Value R 0 PINE3 Port E Input Pins Value R 0 PINE2 Port E Input Pins Value R 0 PINE1 Port E Input Pins Value R 0 PINE0 Port E Input Pins Value R 0 PIN_VALUE_BITF [PORTF:DDRF:PINF] io_port.bmp AVRSimIOPort.SimIOPort PORTF Port F Data Register If PORTFn is written logic one when the PORTF pin n is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTFn has to be written logic zero or the pin has to be configured as an output pin. If PORTFn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTFn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). $11 $31 io_port.bmp N PORTF7 Port F Data Register Value RW 0 PORTF6 Port F Data Register Value RW 0 PORTF5 Port F Data Register Value RW 0 PORTF4 Port F Data Register Value RW 0 PORTF3 Port F Data Register Value RW 0 PORTF2 Port F Data Register Value RW 0 PORTF1 Port F Data Register Value RW 0 PORTF0 Port F Data Register Value RW 0 PORT_DATA_REG_BITF DDRF Port F Data Direction Register The DDFn bit in the DDRF Register selects the direction of the PORTF pin n. If DDFn is written logic one, PFn is configured as an output pin. If DDFn is written logic zero, PFn is configured as an input pin. $10 $30 io_flag.bmp N DDF7 Port F Data Direction Register Value RW 0 DDF6 Port F Data Direction Register Value RW 0 DDF5 Port F Data Direction Register Value RW 0 DDF4 Port F Data Direction Register Value RW 0 DDF3 Port F Data Direction Register Value RW 0 DDF2 Port F Data Direction Register Value RW 0 DDF1 Port F Data Direction Register Value RW 0 DDF0 Port F Data Direction Register Value RW 0 DDR_VALUE_BITF PINF Port F Input Pins Address This register allows access to the PORTF pins independent of the setting of the Data Direction bit DDFn. The port pin can be read through the PINFn Register bit, and writing a logic one to PINFn toggles the value of PORTFn. $0F $2F io_port.bmp N PINF7 Port F Input Pins Value R 0 PINF6 Port F Input Pins Value R 0 PINF5 Port F Input Pins Value R 0 PINF4 Port F Input Pins Value R 0 PINF3 Port F Input Pins Value R 0 PINF2 Port F Input Pins Value R 0 PINF1 Port F Input Pins Value R 0 PINF0 Port F Input Pins Value R 0 PIN_VALUE_BITF [PORTG:DDRG:PING] io_port.bmp AVRSimIOPort.SimIOPort PORTG Port G Data Register If PORTGn is written logic one when the PORTG pin n is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTGn has to be written logic zero or the pin has to be configured as an output pin. If PORTGn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTGn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). $14 $34 io_port.bmp N Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 PORTG5 Port G Data Register Value RW 0 PORTG4 Port G Data Register Value RW 0 PORTG3 Port G Data Register Value RW 0 PORTG2 Port G Data Register Value RW 0 PORTG1 Port G Data Register Value RW 0 PORTG0 Port G Data Register Value RW 0 PORT_DATA_REG2_BITF DDRG Port G Data Direction Register The DDGn bit in the DDRG Register selects the direction of the PORTG pin n. If DDGn is written logic one, PGn is configured as an output pin. If DDGn is written logic zero, PGn is configured as an input pin. $13 $33 io_flag.bmp N Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 DDG5 Port G Data Direction Register Value RW 0 DDG4 Port G Data Direction Register Value RW 0 DDG3 Port G Data Direction Register Value RW 0 DDG2 Port G Data Direction Register Value RW 0 DDG1 Port G Data Direction Register Value RW 0 DDG0 Port G Data Direction Register Value RW 0 DDR_VALUE2_BITF PING Port G Input Pins Address This register allows access to the PORTG pins independent of the setting of the Data Direction bit DDGn. The port pin can be read through the PINGn Register bit, and writing a logic one to PINGn toggles the value of PORTGn. $12 $32 io_port.bmp N Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 PING5 Port G Input Pins Value R 0 PING4 Port G Input Pins Value R 0 PING3 Port G Input Pins Value R 0 PING2 Port G Input Pins Value R 0 PING1 Port G Input Pins Value R 0 PING0 Port G Input Pins Value R 0 PIN_VALUE2_BITF [TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR] io_timer.bmp At8pwm0_01 OCR0B Timer/Counter0 Output Compare Register B The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. $28 $48 io_timer.bmp N OCR0B_7 Output Compare Register RW 0 OCR0B_6 Output Compare Register RW 0 OCR0B_5 Output Compare Register RW 0 OCR0B_4 Output Compare Register RW 0 OCR0B_3 Output Compare Register RW 0 OCR0B_2 Output Compare Register RW 0 OCR0B_1 Output Compare Register RW 0 OCR0B_0 Output Compare Register RW 0 TC0_OCR_BITF OCR0A Timer/Counter0 Output Compare Register The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. $27 $47 io_timer.bmp N OCR0A_7 Output Compare Register RW 0 OCR0A_6 Output Compare Register RW 0 OCR0A_5 Output Compare Register RW 0 OCR0A_4 Output Compare Register RW 0 OCR0A_3 Output Compare Register RW 0 OCR0A_2 Output Compare Register RW 0 OCR0A_1 Output Compare Register RW 0 OCR0A_0 Output Compare Register RW 0 TC0_OCR_BITF TCNT0 Timer/Counter0 Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter0 unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers. $26 $46 io_timer.bmp N TCNT0_7 Timer/Counter0 Byte RW 0 TCNT0_6 Timer/Counter0 Byte RW 0 TCNT0_5 Timer/Counter0 Byte RW 0 TCNT0_4 Timer/Counter0 Byte RW 0 TCNT0_3 Timer/Counter0 Byte RW 0 TCNT0_2 Timer/Counter0 Byte RW 0 TCNT0_1 Timer/Counter0 Byte RW 0 TCNT0_0 Timer/Counter0 Byte RW 0 TC0_TCNT_BITF TCCR0B Timer/Counter0 Control Register B $25 $45 io_flag.bmp Y FOC0A Force Output Compare A The FOC0A bit is only active when the WGM02:0 bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written in a PWM operation mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. W 0 FOC0B Force Output Compare B The FOC0B bit is only active when the WGM02:0 bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written in a PWM operation mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare. A FOC0B strobe will not generate any interrupt nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. W 0 Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 WGM02 Combined with the WGM01:0 bit found in the TCCR0A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see section "Modes of Operation"). RW 0 CS02 Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter0 according to the following table.If external pin modes are used for Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CS01 Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter0 according to the following table.If external pin modes are used for Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CS00 Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter0 according to the following table.If external pin modes are used for Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 TC0_CLK_SEL_3BIT_EXT TCCR0A Timer/Counter0 Control Register A $24 $44 io_flag.bmp Y COM0A1 Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. The following shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). For the functionality in other modes refer to section "Operating Modes". RW 0 COM0A0 Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. The following shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). For the functionality in other modes refer to section "Operating Modes". RW 0 TC0_COM0A_BITF COM0B1 Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. The following shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). For the functionality in other modes refer to section "Operating Modes". RW 0 COM0B0 Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. The following shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). For the functionality in other modes refer to section "Operating Modes". RW 0 TC0_COM0B_BITF Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 WGM01 Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used according to the following table. Modes of operation supported by the Timer/Counter0 unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see section "Modes of Operation" for details). RW 0 WGM00 Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used according to the following table. Modes of operation supported by the Timer/Counter0 unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see section "Modes of Operation" for details). RW 0 TC0_WGM_BITF TIMSK0 Timer/Counter0 Interrupt Mask Register NA $6E io_flag.bmp Y Res4 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res3 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCIE0B Timer/Counter0 Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0B bit is set in the Timer/Counter0 Interrupt Flag Register TIFR0. RW 0 OCIE0A Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter0 Interrupt Flag Register TIFR0. RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs i.e., when the TOV0 bit is set in the Timer/Counter0 Interrupt Flag Register TIFR0. RW 0 TIFR0 Timer/Counter0 Interrupt Flag Register $15 $35 io_flag.bmp Y Res4 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res3 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCF0B Timer/Counter0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0B Output Compare Register. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable) and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed. RW 0 OCF0A Timer/Counter0 Output Compare A Match Flag The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A Output Compare Register. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter Compare A Match Interrupt Enable) and OCF0A are set, the Timer/Counter Compare Match Interrupt is executed. RW 0 TOV0 Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. RW 0 GTCCR General Timer/Counter Control Register $23 $43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during the configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware and the Timer/Counters simultaneously start counting. RW 0 Res4 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res3 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 PSRASY Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. R 0 PSRSYNC PSR10 Prescaler Reset for Synchronous Timer/Counters When this bit is one, the Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 prescaler will be reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the same prescaler and a reset of this prescaler will affect all timers. RW 0 [TIMSK2:TIFR2:TCCR2A:TCCR2B:TCNT2:OCR2A:OCR2B:ASSR:GTCCR] io_timer.bmp At8pwm2_07 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: Single Channel Counter; Clear Timer on Compare Match (Auto Reload); Glitch-free, Phase Correct Pulse Width Modulator (PWM); Frequency Generator; 10-bit Clock Prescaler; Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B); Allows Clocking from External 32 kHz Watch Crystal independent of the I/O Clock. TIMSK2 Timer/Counter Interrupt Mask register NA $70 io_flag.bmp Y Res4 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res3 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCIE2B Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter2 Interrupt Flag Register TIFR2. RW 0 OCIE2A Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter2 Interrupt Flag Register TIFR2. RW 0 TOIE2 TOIE2A Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register TIFR2. RW 0 TIFR2 Timer/Counter Interrupt Flag Register $17 $37 io_flag.bmp Y Res4 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res3 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCF2B Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare Match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare Match Interrupt is executed. RW 0 OCF2A Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare Match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare Match Interrupt is executed. RW 0 TOV2 Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. RW 0 TCCR2A Timer/Counter2 Control Register A NA $B0 io_flag.bmp Y COM2A1 Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. The following table shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Refer to section "Compare Match Output Unit" for a description of the functionality in the other modes. RW 0 COM2A0 Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. The following table shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Refer to section "Compare Match Output Unit" for a description of the functionality in the other modes. RW 0 TC2_COM2A_BITF COM2B1 Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver. When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. The following table shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Refer to section "Compare Match Output Unit" for a description of the functionality in the other modes. RW 0 COM2B0 Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver. When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. The following table shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Refer to section "Compare Match Output Unit" for a description of the functionality in the other modes. RW 0 TC2_COM2B_BITF Res1 Reserved RW 0 Res0 Reserved RW 0 WGM21 Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter2 unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see section "Modes of Operation" for details). RW 0 WGM20 Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter2 unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see section "Modes of Operation" for details). RW 0 TC0_WGM_BITF TCCR2B Timer/Counter2 Control Register B NA $B1 io_flag.bmp Y FOC2A Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written in PWM mode operation. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. RW 0 FOC2B Force Output Compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written in PWM mode operation. When writing a logical one to the FOC2B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the forced compare. A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. RW 0 Res1 Reserved RW 0 Res0 Reserved RW 0 WGM22 Waveform Generation Mode Combined with the WGM21:0 bits found in the TCCR2A Register, this bit controls the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. See description of "TCCR2A - Timer/Counter2 Control Register A" for details. RW 0 CS22 Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter2. If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CS21 Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter2. If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CS20 Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter2. If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW TC2_CLK_SEL_3BIT 0 TCNT2 Timer/Counter2 The Timer/Counter Register gives direct access, both for read and write operations, to the 8-bit counter unit of the Timer/Counter2. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. NA $B2 io_timer.bmp N TCNT27 Timer/Counter2 Byte RW 0 TCNT26 Timer/Counter2 Byte RW 0 TCNT25 Timer/Counter2 Byte RW 0 TCNT24 Timer/Counter2 Byte RW 0 TCNT23 Timer/Counter2 Byte RW 0 TCNT22 Timer/Counter2 Byte RW 0 TCNT21 Timer/Counter2 Byte RW 0 TCNT20 Timer/Counter2 Byte RW 0 TC2_TCNT_BITF OCR2B Timer/Counter2 Output Compare Register B The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2B pin. NA $B4 io_timer.bmp N OCR2B7 Output Compare Register RW 0 OCR2B6 Output Compare Register RW 0 OCR2B5 Output Compare Register RW 0 OCR2B4 Output Compare Register RW 0 OCR2B3 Output Compare Register RW 0 OCR2B2 Output Compare Register RW 0 OCR2B1 Output Compare Register RW 0 OCR2B0 Output Compare Register RW 0 TC2_OCR_BITF OCR2A Timer/Counter2 Output Compare Register A The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. NA $B3 io_timer.bmp N OCR2A7 Output Compare Register RW 0 OCR2A6 Output Compare Register RW 0 OCR2A5 Output Compare Register RW 0 OCR2A4 Output Compare Register RW 0 OCR2A3 Output Compare Register RW 0 OCR2A2 Output Compare Register RW 0 OCR2A1 Output Compare Register RW 0 OCR2A0 Output Compare Register RW 0 TC2_OCR_BITF ASSR Asynchronous Status Register The register ASSR controls the asynchronous clocks for Timer/Counter2 and enables the asynchronous 32kHz clock for the symbol counter. Three bits (AS2,EXCLK,EXCLKAMR) are used to control the clocks. Note, to prevent clock spikes on asynchronous clock wires, every access to ASSR should change only one of the three bits. NA $B6 io_flag.bmp Y EXCLKAMR Enable External Clock Input for AMR The bit EXCLKAMR extends the available clock sources for Timer/Counter2. If this bit is written to one, and asynchronous clock is selected (bit AS2 set), AMR functionality is enabled and Timer/Counter2 is clocked by pin AMR. RW 0 EXCLK Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. RW 0 AS2 Timer/Counter2 Asynchronous Mode When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted. RW 0 TCN2UB Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. R 0 OCR2AUB Timer/Counter2 Output Compare Register A Update Busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. R 0 OCR2BUB Timer/Counter2 Output Compare Register B Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. R 0 TCR2AUB Timer/Counter2 Control Register A Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. R 0 TCR2BUB Timer/Counter2 Control Register B Update Busy When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value. R 0 GTCCR General Timer Counter Control register $23 $43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during the configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware and the Timer/Counters simultaneously start counting. RW 0 PSRASY PSR2 Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. RW 0 [WDTCSR] io_watch.bmp WDTCSR Watchdog Timer Control Register NA $60 io_flag.bmp Y WDIF Watchdog Timeout Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. RW 0 WDIE Watchdog Timeout Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied. RW 0 WDP3 Watchdog Timer Prescaler Bit 3 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The following table also shows approximate time-out values. RW 0 WDCE Watchdog Change Enable This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to one, hardware will clear WDCE after four clock cycles. RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog. WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. RW 0 WDP2 Watch Dog Timer Prescaler bit 2 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The following table also shows approximate time-out values. WDOG_TIMER_PRESCALE_4BITS RW 0 WDP1 Watch Dog Timer Prescaler bit 1 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The following table also shows approximate time-out values. RW 0 WDP0 Watch Dog Timer Prescaler bit 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The following table also shows approximate time-out values. RW 0 [TIMSK5:TIFR5:TCCR5A:TCCR5B:TCCR5C:TCNT5H:TCNT5L:OCR5AH:OCR5AL:OCR5BH:OCR5BL:ICR5H:ICR5L:OCR5CH:OCR5CL] [TCNT5H:TCNT5L];[OCR5AH:OCR5AL];[OCR5BH:OCR5BL];[OCR5CH:OCR5CL];[ICR5H:ICR3L] io_timer.bmp ATmegaAllRFA1_t16pwm5_00.xml TCCR5A Timer/Counter5 Control Register A NA $120 io_flag.bmp Y COM5A1 Compare Output Mode for Channel A The Timer/Counter5 has only limited functionality. Therefore the COM5A1:0 bits do not control the output compare behavior of any pin. The following table shows the COM5A1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM5A0 Compare Output Mode for Channel A The Timer/Counter5 has only limited functionality. Therefore the COM5A1:0 bits do not control the output compare behavior of any pin. The following table shows the COM5A1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC4_COMNX_BITF COM5B1 Compare Output Mode for Channel B The Timer/Counter5 has only limited functionality. Therefore the COM5B1:0 bits do not control the output compare behavior of any pin. The following table shows the COM5B1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM5B0 Compare Output Mode for Channel B The Timer/Counter5 has only limited functionality. Therefore the COM5B1:0 bits do not control the output compare behavior of any pin. The following table shows the COM5B1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC4_COMNX_BITF COM5C1 Compare Output Mode for Channel C The Timer/Counter5 has only limited functionality. Therefore the COM5C1:0 bits do not control the output compare behavior of any pin. The following table shows the COM5C1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM5C0 Compare Output Mode for Channel C The Timer/Counter5 has only limited functionality. Therefore the COM5C1:0 bits do not control the output compare behavior of any pin. The following table shows the COM5C1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC4_COMNX_BITF WGM51 Waveform Generation Mode Combined with the WGM53:2 bits found in the TCCR5B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". Note that Timer/Counter5 has only limited functionality. It cannot be connected to any I/O pin. RW 0 WGM50 Waveform Generation Mode Combined with the WGM53:2 bits found in the TCCR5B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". Note that Timer/Counter5 has only limited functionality. It cannot be connected to any I/O pin. RW 0 TC1_WGMX_BITF TCCR5B Timer/Counter5 Control Register B NA $121 io_flag.bmp Y ICNC5 Input Capture 5 Noise Canceller Timer/Counter5 has only limited functionality. It is not connected to any Input Capture Pin. Therefore this bit has no meaningful function. RW 0 ICES5 Input Capture 5 Edge Select Timer/Counter5 has only limited functionality. It is not connected to any Input Capture Pin. Therefore this bit has no meaningful function. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 WGM53 Waveform Generation Mode Combined with the WGM51:0 bits found in the TCCR5A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". Note that Timer/Counter5 has only limited functionality. It cannot be connected to any I/O pin. RW 0 WGM52 Waveform Generation Mode Combined with the WGM51:0 bits found in the TCCR5A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". Note that Timer/Counter5 has only limited functionality. It cannot be connected to any I/O pin. TC1_WGMX_BITF RW 0 CS52 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter5 according to the following table. External pin modes cannot be used for the Timer/Counter5. RW 0 CS51 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter5 according to the following table. External pin modes cannot be used for the Timer/Counter5. RW 0 CS50 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter5 according to the following table. External pin modes cannot be used for the Timer/Counter5. RW 0 CLK_SEL_3BIT_NOEXT_MEGARF TCCR5C Timer/Counter5 Control Register C NA $122 io_flag.bmp Y FOC5A Force Output Compare for Channel A The FOC5A bit is only active when the WGM53:0 bits specify a non-PWM mode. When writing a logical one to the FOC5A bit, an immediate compare match is forced. Due to the limited functionality of the Timer/Counter5 the match has no direct impact on any output pin. Note that the FOC5A bits are implemented as strobes. Therefore it is the value present in the COM5A1:0 bits that determine the effect of the forced compare. A FOC5A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR5A as TOP. The FOC5A bits are always read as zero. RW 0 FOC5B Force Output Compare for Channel B The FOC5B bit is only active when the WGM53:0 bits specify a non-PWM mode. When writing a logical one to the FOC5B bit, an immediate compare match is forced. Due to the limited functionality of the Timer/Counter5 the match has no direct impact on any output pin. Note that the FOC5B bits are implemented as strobes. Therefore it is the value present in the COM5B1:0 bits that determine the effect of the forced compare. A FOC5B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR5B as TOP. The FOC5B bits are always read as zero. RW 0 FOC5C Force Output Compare for Channel C The FOC5C bit is only active when the WGM53:0 bits specify a non-PWM mode. When writing a logical one to the FOC5C bit, an immediate compare match is forced. Due to the limited functionality of the Timer/Counter5 the match has no direct impact on any output pin. Note that the FOC5C bits are implemented as strobes. Therefore it is the value present in the COM5C1:0 bits that determine the effect of the forced compare. A FOC5C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR5C as TOP. The FOC5C bits are always read as zero. RW 0 Res4 Reserved These bits are reserved for future use. R 0 Res3 Reserved These bits are reserved for future use. R 0 Res2 Reserved These bits are reserved for future use. R 0 Res1 Reserved These bits are reserved for future use. R 0 Res0 Reserved These bits are reserved for future use. R 0 TCNT5H Timer/Counter5 High Byte The two Timer/Counter I/O locations (TCNT5H and TCNT5L, combined TCNT5) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the counter (TCNT5) while the counter is running introduces a risk of missing a compare match between TCNT5 and one of the OCR5x Registers. Writing to the TCNT5 Register blocks (removes) the compare match on the following timer clock for all compare units. NA $125 io_timer.bmp N TCNT5H7 Timer/Counter5 High Byte RW 0 TCNT5H6 Timer/Counter5 High Byte RW 0 TCNT5H5 Timer/Counter5 High Byte RW 0 TCNT5H4 Timer/Counter5 High Byte RW 0 TCNT5H3 Timer/Counter5 High Byte RW 0 TCNT5H2 Timer/Counter5 High Byte RW 0 TCNT5H1 Timer/Counter5 High Byte RW 0 TCNT5H0 Timer/Counter5 High Byte RW 0 TC1_TCNTxHn_BITF TCNT5L Timer/Counter5 Low Byte The two Timer/Counter I/O locations (TCNT5H and TCNT5L, combined TCNT5) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the counter (TCNT5) while the counter is running introduces a risk of missing a compare match between TCNT5 and one of the OCR5x Registers. Writing to the TCNT5 Register blocks (removes) the compare match on the following timer clock for all compare units. NA $124 io_timer.bmp N TCNT5L7 Timer/Counter5 Low Byte RW 0 TCNT5L6 Timer/Counter5 Low Byte RW 0 TCNT5L5 Timer/Counter5 Low Byte RW 0 TCNT5L4 Timer/Counter5 Low Byte RW 0 TCNT5L3 Timer/Counter5 Low Byte RW 0 TCNT5L2 Timer/Counter5 Low Byte RW 0 TCNT5L1 Timer/Counter5 Low Byte RW 0 TCNT5L0 Timer/Counter5 Low Byte RW 0 TC1_TCNTxLn_BITF OCR5AH Timer/Counter5 Output Compare Register A High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT5). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $129 io_timer.bmp N OCR5AH7 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5AH6 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5AH5 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5AH4 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5AH3 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5AH2 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5AH1 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5AH0 Timer/Counter5 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR5AL Timer/Counter5 Output Compare Register A Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT5). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $128 io_timer.bmp N OCR5AL7 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5AL6 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5AL5 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5AL4 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5AL3 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5AL2 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5AL1 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5AL0 Timer/Counter5 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF OCR5BH Timer/Counter5 Output Compare Register B High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT5). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $12B io_timer.bmp N OCR5BH7 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5BH6 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5BH5 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5BH4 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5BH3 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5BH2 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5BH1 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5BH0 Timer/Counter5 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR5BL Timer/Counter5 Output Compare Register B Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT5). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $12A io_timer.bmp N OCR5BL7 Timer/Counter5 Output Compare Register Low Byte R 0 OCR5BL6 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5BL5 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5BL4 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5BL3 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5BL2 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5BL1 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5BL0 Timer/Counter5 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF OCR5CH Timer/Counter5 Output Compare Register C High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT5). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $12D io_timer.bmp N OCR5CH7 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5CH6 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5CH5 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5CH4 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5CH3 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5CH2 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5CH1 Timer/Counter5 Output Compare Register High Byte RW 0 OCR5CH0 Timer/Counter5 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR5CL Timer/Counter5 Output Compare Register C Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT5). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $12C io_timer.bmp N OCR5CL7 Timer/Counter5 Output Compare Register Low Byte R 0 OCR5CL6 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5CL5 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5CL4 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5CL3 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5CL2 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5CL1 Timer/Counter5 Output Compare Register Low Byte RW 0 OCR5CL0 Timer/Counter5 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF ICR5H Timer/Counter5 Input Capture Register High Byte The Timer/Counter5 has only limited functionality. It is not connected to any I/O pin. Therefore the contents of this register is never updated with the counter (TCNT5) value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $127 io_timer.bmp N ICR5H7 Timer/Counter5 Input Capture Register High Byte R 0 ICR5H6 Timer/Counter5 Input Capture Register High Byte R 0 ICR5H5 Timer/Counter5 Input Capture Register High Byte R 0 ICR5H4 Timer/Counter5 Input Capture Register High Byte R 0 ICR5H3 Timer/Counter5 Input Capture Register High Byte R 0 ICR5H2 Timer/Counter5 Input Capture Register High Byte R 0 ICR5H1 Timer/Counter5 Input Capture Register High Byte R 0 ICR5H0 Timer/Counter5 Input Capture Register High Byte R 0 TC1_ICRxnH_BITF ICR5L Timer/Counter5 Input Capture Register Low Byte The Timer/Counter5 has only limited functionality. It is not connected to any I/O pin. Therefore the contents of this register is never updated with the counter (TCNT5) value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $126 io_timer.bmp N ICR5L7 Timer/Counter5 Input Capture Register Low Byte R 0 ICR5L6 Timer/Counter5 Input Capture Register Low Byte R 0 ICR5L5 Timer/Counter5 Input Capture Register Low Byte R 0 ICR5L4 Timer/Counter5 Input Capture Register Low Byte R 0 ICR5L3 Timer/Counter5 Input Capture Register Low Byte R 0 ICR5L2 Timer/Counter5 Input Capture Register Low Byte R 0 ICR5L1 Timer/Counter5 Input Capture Register Low Byte R 0 ICR5L0 Timer/Counter5 Input Capture Register Low Byte R 0 TC1_ICRxnL_BITF TIMSK5 Timer/Counter5 Interrupt Mask Register NA $73 io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 ICIE5 Timer/Counter5 Input Capture Interrupt Enable The Timer/Counter5 has only limited functionality. It does not have an Input Capture pin. Therefore this bit has no useful meaning. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCIE5C Timer/Counter5 Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter5 Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF5C Flag, located in TIFR5, is set. R 0 OCIE5B Timer/Counter5 Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter5 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF5B Flag, located in TIFR5, is set. R 0 OCIE5A Timer/Counter5 Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter5 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF5A Flag, located in TIFR5, is set. RW 0 TOIE5 Timer/Counter5 Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter5 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV5 Flag, located in TIFR5, is set. RW 0 TIFR5 Timer/Counter5 Interrupt Flag Register $1A $3A io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 ICF5 Timer/Counter5 Input Capture Flag The Timer/Counter5 has only limited functionality. It does not have an Input Capture pin. Therefore this bit has no useful meaning. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCF5C Timer/Counter5 Output Compare C Match Flag This flag is set in the timer clock cycle after the counter (TCNT5) value matches the Output Compare Register C (OCR5C). Note that a Forced Output Compare (FOC5C) strobe will not set the OCF5C Flag. OCF5C is automatically cleared when the Output Compare Match C Interrupt Vector is executed. Alternatively, OCF5C can be cleared by writing a logic one to its bit location. RW 0 OCF5B Timer/Counter5 Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT5) value matches the Output Compare Register B (OCR5B). Note that a Forced Output Compare (FOC5B) strobe will not set the OCF5B Flag. OCF5B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF5B can be cleared by writing a logic one to its bit location. RW 0 OCF5A Timer/Counter5 Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT5) value matches the Output Compare Register A (OCR5A). Note that a Forced Output Compare (FOC5A) strobe will not set the OCF5A Flag. OCF5A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF5A can be cleared by writing a logic one to its bit location. RW 0 TOV5 Timer/Counter5 Overflow Flag The setting of this flag is dependent of the WGM53:0 bits setting of the Timer/Counter5 Control Register. In Normal and CTC modes, the TOV5 Flag is set when the timer overflows. TOV5 is automatically cleared when the Timer/Counter5 Overflow Interrupt Vector is executed. Alternatively, TOV5 can be cleared by writing a logic one to its bit location. RW 0 [TIMSK4:TIFR4:TCCR4A:TCCR4B:TCCR4C:TCNT4H:TCNT4L:OCR4AH:OCR4AL:OCR4BH:OCR4BL:ICR4H:ICR4L:OCR4CH:OCR4CL] [TCNT4H:TCNT4L];[OCR4AH:OCR4AL];[OCR4BH:OCR4BL];[OCR4CH:OCR4CL];[ICR4H:ICR4L] io_timer.bmp ATmegaAllRFA1_t16pwm4_00.xml TCCR4A Timer/Counter4 Control Register A NA $A0 io_flag.bmp Y COM4A1 Compare Output Mode for Channel A The Timer/Counter4 has only limited functionality. Therefore the COM4A1:0 bits do not control the output compare behavior of any pin. The following table shows the COM4A1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM4A0 Compare Output Mode for Channel A The Timer/Counter4 has only limited functionality. Therefore the COM4A1:0 bits do not control the output compare behavior of any pin. The following table shows the COM4A1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC4_COMNX_BITF COM4B1 Compare Output Mode for Channel B The Timer/Counter4 has only limited functionality. Therefore the COM4B1:0 bits do not control the output compare behavior of any pin. The following table shows the COM4B1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM4B0 Compare Output Mode for Channel B The Timer/Counter4 has only limited functionality. Therefore the COM4B1:0 bits do not control the output compare behavior of any pin. The following table shows the COM4B1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC4_COMNX_BITF COM4C1 Compare Output Mode for Channel C The Timer/Counter4 has only limited functionality. Therefore the COM4C1:0 bits do not control the output compare behavior of any pin. The following table shows the COM4C1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM4C0 Compare Output Mode for Channel C The Timer/Counter4 has only limited functionality. Therefore the COM4C1:0 bits do not control the output compare behavior of any pin. The following table shows the COM4C1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC4_COMNX_BITF WGM41 Waveform Generation Mode Combined with the WGM43:2 bits found in the TCCR4B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". Note that Timer/Counter4 has only limited functionality. It cannot be connected to any I/O pin. RW 0 WGM40 Waveform Generation Mode Combined with the WGM43:2 bits found in the TCCR4B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". Note that Timer/Counter4 has only limited functionality. It cannot be connected to any I/O pin. RW 0 TC1_WGMX_BITF TCCR4B Timer/Counter4 Control Register B NA $A1 io_flag.bmp Y ICNC4 Input Capture 4 Noise Canceller Timer/Counter4 has only limited functionality. It is not connected to any Input Capture Pin. Therefore this bit has no meaningful function. RW 0 ICES4 Input Capture 4 Edge Select Timer/Counter4 has only limited functionality. It is not connected to any Input Capture Pin. Therefore this bit has no meaningful function. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 WGM43 Waveform Generation Mode Combined with the WGM41:0 bits found in the TCCR4A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". Note that Timer/Counter4 has only limited functionality. It cannot be connected to any I/O pin. RW 0 WGM42 Waveform Generation Mode Combined with the WGM41:0 bits found in the TCCR4A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". Note that Timer/Counter4 has only limited functionality. It cannot be connected to any I/O pin. TC1_WGMX_BITF RW 0 CS42 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter4 according to the following table. External pin modes cannot be used for the Timer/Counter4. RW 0 CS41 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter4 according to the following table. External pin modes cannot be used for the Timer/Counter4. RW 0 CS40 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter4 according to the following table. External pin modes cannot be used for the Timer/Counter4. RW 0 CLK_SEL_3BIT_NOEXT_MEGARF TCCR4C Timer/Counter4 Control Register C NA $A2 io_flag.bmp Y FOC4A Force Output Compare for Channel A The FOC4A bit is only active when the WGM43:0 bits specify a non-PWM mode. When writing a logical one to the FOC4A bit, an immediate compare match is forced. Due to the limited functionality of the Timer/Counter4 the match has no direct impact on any output pin. Note that the FOC4A bits are implemented as strobes. Therefore it is the value present in the COM4A1:0 bits that determine the effect of the forced compare. A FOC4A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR4A as TOP. The FOC4A bits are always read as zero. RW 0 FOC4B Force Output Compare for Channel B The FOC4B bit is only active when the WGM43:0 bits specify a non-PWM mode. When writing a logical one to the FOC4B bit, an immediate compare match is forced. Due to the limited functionality of the Timer/Counter4 the match has no direct impact on any output pin. Note that the FOC4B bits are implemented as strobes. Therefore it is the value present in the COM4B1:0 bits that determine the effect of the forced compare. A FOC4B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR4B as TOP. The FOC4B bits are always read as zero. RW 0 FOC4C Force Output Compare for Channel C The FOC4C bit is only active when the WGM43:0 bits specify a non-PWM mode. When writing a logical one to the FOC4C bit, an immediate compare match is forced. Due to the limited functionality of the Timer/Counter4 the match has no direct impact on any output pin. Note that the FOC4C bits are implemented as strobes. Therefore it is the value present in the COM4C1:0 bits that determine the effect of the forced compare. A FOC4C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR4C as TOP. The FOC4C bits are always read as zero. RW 0 Res4 Reserved These bits are reserved for future use. R 0 Res3 Reserved These bits are reserved for future use. R 0 Res2 Reserved These bits are reserved for future use. R 0 Res1 Reserved These bits are reserved for future use. R 0 Res0 Reserved These bits are reserved for future use. R 0 TCNT4H Timer/Counter4 High Byte The two Timer/Counter I/O locations (TCNT4H and TCNT4L, combined TCNT4) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the counter (TCNT4) while the counter is running introduces a risk of missing a compare match between TCNT4 and one of the OCR4x Registers. Writing to the TCNT4 Register blocks (removes) the compare match on the following timer clock for all compare units. NA $A5 io_timer.bmp N TCNT4H7 Timer/Counter4 High Byte RW 0 TCNT4H6 Timer/Counter4 High Byte RW 0 TCNT4H5 Timer/Counter4 High Byte RW 0 TCNT4H4 Timer/Counter4 High Byte RW 0 TCNT4H3 Timer/Counter4 High Byte RW 0 TCNT4H2 Timer/Counter4 High Byte RW 0 TCNT4H1 Timer/Counter4 High Byte RW 0 TCNT4H0 Timer/Counter4 High Byte RW 0 TC1_TCNTxHn_BITF TCNT4L Timer/Counter4 Low Byte The two Timer/Counter I/O locations (TCNT4H and TCNT4L, combined TCNT4) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the counter (TCNT4) while the counter is running introduces a risk of missing a compare match between TCNT4 and one of the OCR4x Registers. Writing to the TCNT4 Register blocks (removes) the compare match on the following timer clock for all compare units. NA $A4 io_timer.bmp N TCNT4L7 Timer/Counter4 Low Byte RW 0 TCNT4L6 Timer/Counter4 Low Byte RW 0 TCNT4L5 Timer/Counter4 Low Byte RW 0 TCNT4L4 Timer/Counter4 Low Byte RW 0 TCNT4L3 Timer/Counter4 Low Byte RW 0 TCNT4L2 Timer/Counter4 Low Byte RW 0 TCNT4L1 Timer/Counter4 Low Byte RW 0 TCNT4L0 Timer/Counter4 Low Byte RW 0 TC1_TCNTxLn_BITF OCR4AH Timer/Counter4 Output Compare Register A High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT4). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $A9 io_timer.bmp N OCR4AH7 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4AH6 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4AH5 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4AH4 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4AH3 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4AH2 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4AH1 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4AH0 Timer/Counter4 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR4AL Timer/Counter4 Output Compare Register A Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT4). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $A8 io_timer.bmp N OCR4AL7 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4AL6 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4AL5 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4AL4 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4AL3 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4AL2 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4AL1 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4AL0 Timer/Counter4 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF OCR4BH Timer/Counter4 Output Compare Register B High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT4). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $AB io_timer.bmp N OCR4BH7 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4BH6 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4BH5 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4BH4 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4BH3 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4BH2 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4BH1 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4BH0 Timer/Counter4 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR4BL Timer/Counter4 Output Compare Register B Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT4). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $AA io_timer.bmp N OCR4BL7 Timer/Counter4 Output Compare Register Low Byte R 0 OCR4BL6 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4BL5 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4BL4 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4BL3 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4BL2 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4BL1 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4BL0 Timer/Counter4 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF OCR4CH Timer/Counter4 Output Compare Register C High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT4). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $AD io_timer.bmp N OCR4CH7 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4CH6 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4CH5 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4CH4 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4CH3 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4CH2 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4CH1 Timer/Counter4 Output Compare Register High Byte RW 0 OCR4CH0 Timer/Counter4 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR4CL Timer/Counter4 Output Compare Register C Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT4). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $AC io_timer.bmp N OCR4CL7 Timer/Counter4 Output Compare Register Low Byte R 0 OCR4CL6 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4CL5 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4CL4 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4CL3 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4CL2 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4CL1 Timer/Counter4 Output Compare Register Low Byte RW 0 OCR4CL0 Timer/Counter4 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF ICR4H Timer/Counter4 Input Capture Register High Byte The Timer/Counter4 has only limited functionality. It is not connected to any I/O pin. Therefore the contents of this register is never updated with the counter (TCNT4) value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $A7 io_timer.bmp N ICR4H7 Timer/Counter4 Input Capture Register High Byte R 0 ICR4H6 Timer/Counter4 Input Capture Register High Byte R 0 ICR4H5 Timer/Counter4 Input Capture Register High Byte R 0 ICR4H4 Timer/Counter4 Input Capture Register High Byte R 0 ICR4H3 Timer/Counter4 Input Capture Register High Byte R 0 ICR4H2 Timer/Counter4 Input Capture Register High Byte R 0 ICR4H1 Timer/Counter4 Input Capture Register High Byte R 0 ICR4H0 Timer/Counter4 Input Capture Register High Byte R 0 TC1_ICRxnH_BITF ICR4L Timer/Counter4 Input Capture Register Low Byte The Timer/Counter4 has only limited functionality. It is not connected to any I/O pin. Therefore the contents of this register is never updated with the counter (TCNT4) value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $A6 io_timer.bmp N ICR4L7 Timer/Counter4 Input Capture Register Low Byte R 0 ICR4L6 Timer/Counter4 Input Capture Register Low Byte R 0 ICR4L5 Timer/Counter4 Input Capture Register Low Byte R 0 ICR4L4 Timer/Counter4 Input Capture Register Low Byte R 0 ICR4L3 Timer/Counter4 Input Capture Register Low Byte R 0 ICR4L2 Timer/Counter4 Input Capture Register Low Byte R 0 ICR4L1 Timer/Counter4 Input Capture Register Low Byte R 0 ICR4L0 Timer/Counter4 Input Capture Register Low Byte R 0 TC1_ICRxnL_BITF TIMSK4 Timer/Counter4 Interrupt Mask Register NA $72 io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 ICIE4 Timer/Counter4 Input Capture Interrupt Enable The Timer/Counter4 has only limited functionality. It does not have an Input Capture pin. Therefore this bit has no useful meaning. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCIE4C Timer/Counter4 Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter4 Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF4C Flag, located in TIFR4, is set. R 0 OCIE4B Timer/Counter4 Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter4 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF4B Flag, located in TIFR4, is set. R 0 OCIE4A Timer/Counter4 Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter4 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF4A Flag, located in TIFR4, is set. RW 0 TOIE4 Timer/Counter4 Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter4 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV4 Flag, located in TIFR4, is set. RW 0 TIFR4 Timer/Counter4 Interrupt Flag Register $19 $39 io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 ICF4 Timer/Counter4 Input Capture Flag The Timer/Counter4 has only limited functionality. It does not have an Input Capture pin. Therefore this bit has no useful meaning. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCF4C Timer/Counter4 Output Compare C Match Flag This flag is set in the timer clock cycle after the counter (TCNT4) value matches the Output Compare Register C (OCR4C). Note that a Forced Output Compare (FOC4C) strobe will not set the OCF4C Flag. OCF4C is automatically cleared when the Output Compare Match C Interrupt Vector is executed. Alternatively, OCF4C can be cleared by writing a logic one to its bit location. RW 0 OCF4B Timer/Counter4 Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT4) value matches the Output Compare Register B (OCR4B). Note that a Forced Output Compare (FOC4B) strobe will not set the OCF4B Flag. OCF4B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF4B can be cleared by writing a logic one to its bit location. RW 0 OCF4A Timer/Counter4 Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT4) value matches the Output Compare Register A (OCR4A). Note that a Forced Output Compare (FOC4A) strobe will not set the OCF4A Flag. OCF4A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF4A can be cleared by writing a logic one to its bit location. RW 0 TOV4 Timer/Counter4 Overflow Flag The setting of this flag is dependent of the WGM43:0 bits setting of the Timer/Counter4 Control Register. In Normal and CTC modes, the TOV4 Flag is set when the timer overflows. TOV4 is automatically cleared when the Timer/Counter4 Overflow Interrupt Vector is executed. Alternatively, TOV4 can be cleared by writing a logic one to its bit location. RW 0 [TIMSK3:TIFR3:TCCR3A:TCCR3B:TCCR3C:TCNT3H:TCNT3L:OCR3AH:OCR3AL:OCR3BH:OCR3BL:ICR3H:ICR3L:OCR3CH:OCR3CL] [TCNT3H:TCNT3L];[OCR3AH:OCR3AL];[OCR3BH:OCR3BL];[OCR3CH:OCR3CL];[ICR3H:ICR3L] io_timer.bmp ATmegaAllRFA1_t16pwm3_03.xml TCCR3A Timer/Counter3 Control Register A NA $90 io_flag.bmp Y COM3A1 Compare Output Mode for Channel A The COM3A1:0 bits control the output compare behavior of pin OC3A. If one or both of the COM3A1:0 bits are written to one, the OC3A output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC3A pin must be set in order to enable the output driver. When the OC3A is connected to the pin, the function of the COM3A1:0 bits is dependent of the WGM33:0 bits setting. The following table shows the COM3A1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM3A0 Compare Output Mode for Channel A The COM3A1:0 bits control the output compare behavior of pin OC3A. If one or both of the COM3A1:0 bits are written to one, the OC3A output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC3A pin must be set in order to enable the output driver. When the OC3A is connected to the pin, the function of the COM3A1:0 bits is dependent of the WGM33:0 bits setting. The following table shows the COM3A1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC1_COMNX_BITF COM3B1 Compare Output Mode for Channel B The COM3B1:0 bits control the output compare behavior of pin OC3B. If one or both of the COM3B1:0 bits are written to one, the OC3B output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC3B pin must be set in order to enable the output driver. When the OC3B is connected to the pin, the function of the COM3B1:0 bits is dependent of the WGM33:0 bits setting. The following table shows the COM3B1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM3B0 Compare Output Mode for Channel B The COM3B1:0 bits control the output compare behavior of pin OC3B. If one or both of the COM3B1:0 bits are written to one, the OC3B output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC3B pin must be set in order to enable the output driver. When the OC3B is connected to the pin, the function of the COM3B1:0 bits is dependent of the WGM33:0 bits setting. The following table shows the COM3B1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC1_COMNX_BITF COM3C1 Compare Output Mode for Channel C The COM3C1:0 bits control the output compare behavior of pin OC3C. If one or both of the COM3C1:0 bits are written to one, the OC3C output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC3C pin must be set in order to enable the output driver. When the OC3C is connected to the pin, the function of the COM3C1:0 bits is dependent of the WGM33:0 bits setting. The following table shows the COM3C1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM3C0 Compare Output Mode for Channel C The COM3C1:0 bits control the output compare behavior of pin OC3C. If one or both of the COM3C1:0 bits are written to one, the OC3C output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC3C pin must be set in order to enable the output driver. When the OC3C is connected to the pin, the function of the COM3C1:0 bits is dependent of the WGM33:0 bits setting. The following table shows the COM3C1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC1_COMNX_BITF WGM31 Waveform Generation Mode Combined with the WGM33:2 bits found in the TCCR3B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". RW 0 WGM30 Waveform Generation Mode Combined with the WGM33:2 bits found in the TCCR3B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". RW 0 TC1_WGMX_BITF TCCR3B Timer/Counter3 Control Register B NA $91 io_flag.bmp Y ICNC3 Input Capture 3 Noise Canceller Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP3) is filtered. The filter function requires four successive equal valued samples of the ICP3 pin for changing its output. The input capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. RW 0 ICES3 Input Capture 3 Edge Select This bit selects which edge on the Input Capture Pin (ICP3) that is used to trigger a capture event. When the ICES3 bit is written to zero, a falling (negative) edge is used as trigger. When the ICES3 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES3 setting, the counter value is copied into the Input Capture Register (ICR3). The event will also set the Input Capture Flag (ICF3). This can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR3 is used as TOP value (see description of the WGM33:0 bits located in the TCCR3A and the TCCR3B Register), the ICP3 is disconnected and consequently the input capture function is disabled. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 WGM33 Waveform Generation Mode Combined with the WGM31:0 bits found in the TCCR3A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". RW 0 WGM32 Waveform Generation Mode Combined with the WGM31:0 bits found in the TCCR3A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". TC1_WGMX_BITF RW 0 CS32 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter3 according to the following table. If external pin modes are used for the Timer/Counter3, transitions on the T3 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CS31 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter3 according to the following table. If external pin modes are used for the Timer/Counter3, transitions on the T3 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CS30 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter3 according to the following table. If external pin modes are used for the Timer/Counter3, transitions on the T3 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CLK_SEL_3BIT_EXT_MEGARF TCCR3C Timer/Counter3 Control Register C NA $92 io_flag.bmp Y FOC3A Force Output Compare for Channel A The FOC3A bit is only active when the WGM33:0 bits specify a non-PWM mode. When writing a logical one to the FOC3A bit, an immediate compare match is forced on the waveform generation unit. The OC3A output is changed according to its COM3A1:0 bits setting. Note that the FOC3A bits are implemented as strobes. Therefore it is the value present in the COM3A1:0 bits that determine the effect of the forced compare. A FOC3A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR3A as TOP. The FOC3A bits are always read as zero. RW 0 FOC3B Force Output Compare for Channel B The FOC3B bit is only active when the WGM33:0 bits specify a non-PWM mode. When writing a logical one to the FOC3B bit, an immediate compare match is forced on the waveform generation unit. The OC3B output is changed according to its COM3B1:0 bits setting. Note that the FOC3B bits are implemented as strobes. Therefore it is the value present in the COM3B1:0 bits that determine the effect of the forced compare. A FOC3B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1B as TOP. The FOC3B bits are always read as zero. RW 0 FOC3C Force Output Compare for Channel C The FOC3C bit is only active when the WGM33:0 bits specify a non-PWM mode. When writing a logical one to the FOC3C bit, an immediate compare match is forced on the waveform generation unit. The OC3C output is changed according to its COM3C1:0 bits setting. Note that the FOC3C bits are implemented as strobes. Therefore it is the value present in the COM3C1:0 bits that determine the effect of the forced compare. A FOC3C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR3C as TOP. The FOC3C bits are always read as zero. RW 0 Res4 Reserved These bits are reserved for future use. R 0 Res3 Reserved These bits are reserved for future use. R 0 Res2 Reserved These bits are reserved for future use. R 0 Res1 Reserved These bits are reserved for future use. R 0 Res0 Reserved These bits are reserved for future use. R 0 TCNT3H Timer/Counter3 High Byte The two Timer/Counter I/O locations (TCNT3H and TCNT3L, combined TCNT3) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the counter (TCNT3) while the counter is running introduces a risk of missing a compare match between TCNT3 and one of the OCR3x Registers. Writing to the TCNT3 Register blocks (removes) the compare match on the following timer clock for all compare units. NA $95 io_timer.bmp N TCNT3H7 Timer/Counter3 High Byte RW 0 TCNT3H6 Timer/Counter3 High Byte RW 0 TCNT3H5 Timer/Counter3 High Byte RW 0 TCNT3H4 Timer/Counter3 High Byte RW 0 TCNT3H3 Timer/Counter3 High Byte RW 0 TCNT3H2 Timer/Counter3 High Byte RW 0 TCNT3H1 Timer/Counter3 High Byte RW 0 TCNT3H0 Timer/Counter3 High Byte RW 0 TC1_TCNTxHn_BITF TCNT3L Timer/Counter3 Low Byte The two Timer/Counter I/O locations (TCNT3H and TCNT3L, combined TCNT3) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the counter (TCNT3) while the counter is running introduces a risk of missing a compare match between TCNT3 and one of the OCR3x Registers. Writing to the TCNT3 Register blocks (removes) the compare match on the following timer clock for all compare units. NA $94 io_timer.bmp N TCNT3L7 Timer/Counter3 Low Byte RW 0 TCNT3L6 Timer/Counter3 Low Byte RW 0 TCNT3L5 Timer/Counter3 Low Byte RW 0 TCNT3L4 Timer/Counter3 Low Byte RW 0 TCNT3L3 Timer/Counter3 Low Byte RW 0 TCNT3L2 Timer/Counter3 Low Byte RW 0 TCNT3L1 Timer/Counter3 Low Byte RW 0 TCNT3L0 Timer/Counter3 Low Byte RW 0 TC1_TCNTxLn_BITF OCR3AH Timer/Counter3 Output Compare Register A High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC3A pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $99 io_timer.bmp N OCR3AH7 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3AH6 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3AH5 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3AH4 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3AH3 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3AH2 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3AH1 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3AH0 Timer/Counter3 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR3AL Timer/Counter3 Output Compare Register A Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC3A pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $98 io_timer.bmp N OCR3AL7 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3AL6 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3AL5 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3AL4 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3AL3 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3AL2 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3AL1 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3AL0 Timer/Counter3 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF OCR3BH Timer/Counter3 Output Compare Register B High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC3B pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $9B io_timer.bmp N OCR3BH7 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3BH6 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3BH5 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3BH4 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3BH3 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3BH2 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3BH1 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3BH0 Timer/Counter3 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR3BL Timer/Counter3 Output Compare Register B Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC3B pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $9A io_timer.bmp N OCR3BL7 Timer/Counter3 Output Compare Register Low Byte R 0 OCR3BL6 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3BL5 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3BL4 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3BL3 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3BL2 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3BL1 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3BL0 Timer/Counter3 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF OCR3CH Timer/Counter3 Output Compare Register C High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC3C pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $9D io_timer.bmp N OCR3CH7 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3CH6 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3CH5 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3CH4 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3CH3 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3CH2 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3CH1 Timer/Counter3 Output Compare Register High Byte RW 0 OCR3CH0 Timer/Counter3 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR3CL Timer/Counter3 Output Compare Register C Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC3C pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $9C io_timer.bmp N OCR3CL7 Timer/Counter3 Output Compare Register Low Byte R 0 OCR3CL6 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3CL5 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3CL4 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3CL3 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3CL2 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3CL1 Timer/Counter3 Output Compare Register Low Byte RW 0 OCR3CL0 Timer/Counter3 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF ICR3H Timer/Counter3 Input Capture Register High Byte The Input Capture Register is updated with the counter (TCNT3) value each time an event occurs on the ICP3 pin. The Input Capture Register can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $97 io_timer.bmp N ICR3H7 Timer/Counter3 Input Capture Register High Byte R 0 ICR3H6 Timer/Counter3 Input Capture Register High Byte R 0 ICR3H5 Timer/Counter3 Input Capture Register High Byte R 0 ICR3H4 Timer/Counter3 Input Capture Register High Byte R 0 ICR3H3 Timer/Counter3 Input Capture Register High Byte R 0 ICR3H2 Timer/Counter3 Input Capture Register High Byte R 0 ICR3H1 Timer/Counter3 Input Capture Register High Byte R 0 ICR3H0 Timer/Counter3 Input Capture Register High Byte R 0 TC1_ICRxnH_BITF ICR3L Timer/Counter3 Input Capture Register Low Byte The Input Capture Register is updated with the counter (TCNT3) value each time an event occurs on the ICP3 pin. The Input Capture Register can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $96 io_timer.bmp N ICR3L7 Timer/Counter3 Input Capture Register Low Byte R 0 ICR3L6 Timer/Counter3 Input Capture Register Low Byte R 0 ICR3L5 Timer/Counter3 Input Capture Register Low Byte R 0 ICR3L4 Timer/Counter3 Input Capture Register Low Byte R 0 ICR3L3 Timer/Counter3 Input Capture Register Low Byte R 0 ICR3L2 Timer/Counter3 Input Capture Register Low Byte R 0 ICR3L1 Timer/Counter3 Input Capture Register Low Byte R 0 ICR3L0 Timer/Counter3 Input Capture Register Low Byte R 0 TC1_ICRxnL_BITF TIMSK3 Timer/Counter3 Interrupt Mask Register NA $71 io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 ICIE3 Timer/Counter3 Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICF3 Flag, located in TIFR3, is set. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCIE3C Timer/Counter3 Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF3C Flag, located in TIFR3, is set. R 0 OCIE3B Timer/Counter3 Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF3B Flag, located in TIFR3, is set. R 0 OCIE3A Timer/Counter3 Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF3A Flag, located in TIFR3, is set. RW 0 TOIE3 Timer/Counter3 Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV3 Flag, located in TIFR3, is set. RW 0 TIFR3 Timer/Counter3 Interrupt Flag Register $18 $38 io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 ICF3 Timer/Counter3 Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is set by the WGM33:0 to be used as the TOP value, the ICF3 Flag is set when the counter reaches the TOP value. ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF3 can be cleared by writing a logic one to its bit location. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCF3C Timer/Counter3 Output Compare C Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register C (OCR3C). Note that a Forced Output Compare (FOC3C) strobe will not set the OCF3C Flag. OCF3C is automatically cleared when the Output Compare Match C Interrupt Vector is executed. Alternatively, OCF3C can be cleared by writing a logic one to its bit location. RW 0 OCF3B Timer/Counter3 Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register B (OCR3B). Note that a Forced Output Compare (FOC3B) strobe will not set the OCF3B Flag. OCF3B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF3B can be cleared by writing a logic one to its bit location. RW 0 OCF3A Timer/Counter3 Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register A (OCR3A). Note that a Forced Output Compare (FOC3A) strobe will not set the OCF3A Flag. OCF3A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF3A can be cleared by writing a logic one to its bit location. RW 0 TOV3 Timer/Counter3 Overflow Flag The setting of this flag is dependent of the WGM33:0 bits setting of the Timer/Counter3 Control Register. In Normal and CTC modes, the TOV3 Flag is set when the timer overflows. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit location. RW 0 [TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L:OCR1CH:OCR1CL] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[OCR1CH:OCR1CL];[ICR1H:ICR1L] io_timer.bmp ATmegaAllRFA1_t16pwm1_14.xml TCCR1A Timer/Counter1 Control Register A NA $80 io_flag.bmp Y COM1A1 Compare Output Mode for Channel A The COM1A1:0 bits control the output compare behavior of pin OC1A. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC1A pin must be set in order to enable the output driver. When the OC1A is connected to the pin, the function of the COM1A1:0 bits is dependent of the WGM13:0 bits setting. The following table shows the COM1A1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM1A0 Compare Output Mode for Channel A The COM1A1:0 bits control the output compare behavior of pin OC1A. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC1A pin must be set in order to enable the output driver. When the OC1A is connected to the pin, the function of the COM1A1:0 bits is dependent of the WGM13:0 bits setting. The following table shows the COM1A1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC1_COMNX_BITF COM1B1 Compare Output Mode for Channel B The COM1B1:0 bits control the output compare behavior of pin OC1B. If one or both of the COM1B1:0 bits are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC1B pin must be set in order to enable the output driver. When the OC1A is connected to the pin, the function of the COM1B1:0 bits is dependent of the WGM13:0 bits setting. The following table shows the COM1B1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM1B0 Compare Output Mode for Channel B The COM1B1:0 bits control the output compare behavior of pin OC1B. If one or both of the COM1B1:0 bits are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC1B pin must be set in order to enable the output driver. When the OC1A is connected to the pin, the function of the COM1B1:0 bits is dependent of the WGM13:0 bits setting. The following table shows the COM1B1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC1_COMNX_BITF COM1C1 Compare Output Mode for Channel C The COM1C1:0 bits control the output compare behavior of pin OC1C. If one or both of the COM1C1:0 bits are written to one, the OC1C output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC1C pin must be set in order to enable the output driver. When the OC1A is connected to the pin, the function of the COM1C1:0 bits is dependent of the WGM13:0 bits setting. The following table shows the COM1C1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 COM1C0 Compare Output Mode for Channel C The COM1C1:0 bits control the output compare behavior of pin OC1C. If one or both of the COM1C1:0 bits are written to one, the OC1C output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC1C pin must be set in order to enable the output driver. When the OC1A is connected to the pin, the function of the COM1C1:0 bits is dependent of the WGM13:0 bits setting. The following table shows the COM1C1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". RW 0 TC1_COMNX_BITF WGM11 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". RW 0 WGM10 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". RW 0 TC1_WGMX_BITF TCCR1B Timer/Counter1 Control Register B NA $81 io_flag.bmp Y ICNC1 Input Capture 1 Noise Canceller Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The input capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. RW 0 ICES1 Input Capture 1 Edge Select This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger. When the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1). This can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the input capture function is disabled. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 WGM13 Waveform Generation Mode Combined with the WGM11:0 bits found in the TCCR1A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". RW 0 WGM12 Waveform Generation Mode Combined with the WGM11:0 bits found in the TCCR1A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more information on the different modes see section "Modes of Operation". TC1_WGMX_BITF RW 0 CS12 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter1 according to the following table. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CS11 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter1 according to the following table. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CS10 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter1 according to the following table. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. RW 0 CLK_SEL_3BIT_EXT_MEGARF TCCR1C Timer/Counter1 Control Register C NA $82 io_flag.bmp Y FOC1A Force Output Compare for Channel A The FOC1A bit is only active when the WGM13:0 bits specify a non-PWM mode. When writing a logical one to the FOC1A bit, an immediate compare match is forced on the waveform generation unit. The OC1A output is changed according to its COM1A1:0 bits setting. Note that the FOC1A bits are implemented as strobes. Therefore it is the value present in the COM1A1:0 bits that determine the effect of the forced compare. A FOC1A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1A as TOP. The FOC1A bits are always read as zero. RW 0 FOC1B Force Output Compare for Channel B The FOC1B bit is only active when the WGM13:0 bits specify a non-PWM mode. When writing a logical one to the FOC1B bit, an immediate compare match is forced on the waveform generation unit. The OC1B output is changed according to its COM1B1:0 bits setting. Note that the FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1B1:0 bits that determine the effect of the forced compare. A FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1B as TOP. The FOC1B bits are always read as zero. RW 0 FOC1C Force Output Compare for Channel C The FOC1C bit is only active when the WGM13:0 bits specify a non-PWM mode. When writing a logical one to the FOC1C bit, an immediate compare match is forced on the waveform generation unit. The OC1C output is changed according to its COM1C1:0 bits setting. Note that the FOC1C bits are implemented as strobes. Therefore it is the value present in the COM1C1:0 bits that determine the effect of the forced compare. A FOC1C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1C as TOP. The FOC1C bits are always read as zero. RW 0 Res4 Reserved These bits are reserved for future use. R 0 Res3 Reserved These bits are reserved for future use. R 0 Res2 Reserved These bits are reserved for future use. R 0 Res1 Reserved These bits are reserved for future use. R 0 Res0 Reserved These bits are reserved for future use. R 0 TCNT1H Timer/Counter1 High Byte The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. NA $85 io_timer.bmp N TCNT1H7 Timer/Counter1 High Byte RW 0 TCNT1H6 Timer/Counter1 High Byte RW 0 TCNT1H5 Timer/Counter1 High Byte RW 0 TCNT1H4 Timer/Counter1 High Byte RW 0 TCNT1H3 Timer/Counter1 High Byte RW 0 TCNT1H2 Timer/Counter1 High Byte RW 0 TCNT1H1 Timer/Counter1 High Byte RW 0 TCNT1H0 Timer/Counter1 High Byte RW 0 TC1_TCNTxHn_BITF TCNT1L Timer/Counter1 Low Byte The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. NA $84 io_timer.bmp N TCNT1L7 Timer/Counter1 Low Byte RW 0 TCNT1L6 Timer/Counter1 Low Byte RW 0 TCNT1L5 Timer/Counter1 Low Byte RW 0 TCNT1L4 Timer/Counter1 Low Byte RW 0 TCNT1L3 Timer/Counter1 Low Byte RW 0 TCNT1L2 Timer/Counter1 Low Byte RW 0 TCNT1L1 Timer/Counter1 Low Byte RW 0 TCNT1L0 Timer/Counter1 Low Byte RW 0 TC1_TCNTxLn_BITF OCR1AH Timer/Counter1 Output Compare Register A High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1A pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $89 io_timer.bmp N OCR1AH7 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1AH6 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1AH5 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1AH4 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1AH3 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1AH2 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1AH1 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1AH0 Timer/Counter1 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR1AL Timer/Counter1 Output Compare Register A Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1A pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $88 io_timer.bmp N OCR1AL7 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1AL6 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1AL5 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1AL4 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1AL3 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1AL2 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1AL1 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1AL0 Timer/Counter1 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF OCR1BH Timer/Counter1 Output Compare Register B High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1B pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $8B io_timer.bmp N OCR1BH7 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1BH6 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1BH5 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1BH4 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1BH3 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1BH2 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1BH1 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1BH0 Timer/Counter1 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR1BL Timer/Counter1 Output Compare Register B Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1B pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $8A io_timer.bmp N OCR1BL7 Timer/Counter1 Output Compare Register Low Byte R 0 OCR1BL6 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1BL5 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1BL4 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1BL3 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1BL2 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1BL1 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1BL0 Timer/Counter1 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF OCR1CH Timer/Counter1 Output Compare Register C High Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1C pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $8D io_timer.bmp N OCR1CH7 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1CH6 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1CH5 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1CH4 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1CH3 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1CH2 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1CH1 Timer/Counter1 Output Compare Register High Byte RW 0 OCR1CH0 Timer/Counter1 Output Compare Register High Byte RW 0 TC1_OCRxnH_BITF OCR1CL Timer/Counter1 Output Compare Register C Low Byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1C pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $8C io_timer.bmp N OCR1CL7 Timer/Counter1 Output Compare Register Low Byte R 0 OCR1CL6 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1CL5 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1CL4 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1CL3 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1CL2 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1CL1 Timer/Counter1 Output Compare Register Low Byte RW 0 OCR1CL0 Timer/Counter1 Output Compare Register Low Byte RW 0 TC1_OCRxnL_BITF ICR1H Timer/Counter1 Input Capture Register High Byte The Input Capture Register is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin or on the Analog Comparator output. The Input Capture Register can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $87 io_timer.bmp N ICR1H7 Timer/Counter1 Input Capture Register High Byte R 0 ICR1H6 Timer/Counter1 Input Capture Register High Byte R 0 ICR1H5 Timer/Counter1 Input Capture Register High Byte R 0 ICR1H4 Timer/Counter1 Input Capture Register High Byte R 0 ICR1H3 Timer/Counter1 Input Capture Register High Byte R 0 ICR1H2 Timer/Counter1 Input Capture Register High Byte R 0 ICR1H1 Timer/Counter1 Input Capture Register High Byte R 0 ICR1H0 Timer/Counter1 Input Capture Register High Byte R 0 TC1_ICRxnH_BITF ICR1L Timer/Counter1 Input Capture Register Low Byte The Input Capture Register is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin or on the Analog Comparator output. The Input Capture Register can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" for details. NA $86 io_timer.bmp N ICR1L7 Timer/Counter1 Input Capture Register Low Byte R 0 ICR1L6 Timer/Counter1 Input Capture Register Low Byte R 0 ICR1L5 Timer/Counter1 Input Capture Register Low Byte R 0 ICR1L4 Timer/Counter1 Input Capture Register Low Byte R 0 ICR1L3 Timer/Counter1 Input Capture Register Low Byte R 0 ICR1L2 Timer/Counter1 Input Capture Register Low Byte R 0 ICR1L1 Timer/Counter1 Input Capture Register Low Byte R 0 ICR1L0 Timer/Counter1 Input Capture Register Low Byte R 0 TC1_ICRxnL_BITF TIMSK1 Timer/Counter1 Interrupt Mask Register NA $6F io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 ICIE1 Timer/Counter1 Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICF1 Flag, located in TIFR1, is set. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCIE1C Timer/Counter1 Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF1C Flag, located in TIFR1, is set. R 0 OCIE1B Timer/Counter1 Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF1B Flag, located in TIFR1, is set. R 0 OCIE1A Timer/Counter1 Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF1A Flag, located in TIFR1, is set. RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV1 Flag, located in TIFR1, is set. RW 0 TIFR1 Timer/Counter1 Interrupt Flag Register $16 $36 io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 ICF1 Timer/Counter1 Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. RW 0 Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 OCF1C Timer/Counter1 Output Compare C Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register C (OCR1C). Note that a Forced Output Compare (FOC1C) strobe will not set the OCF1C Flag. OCF1C is automatically cleared when the Output Compare Match C Interrupt Vector is executed. Alternatively, OCF1C can be cleared by writing a logic one to its bit location. RW 0 OCF1B Timer/Counter1 Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. RW 0 OCF1A Timer/Counter1 Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. RW 0 TOV1 Timer/Counter1 Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting of the Timer/Counter1 Control Register. In Normal and CTC modes, the TOV1 Flag is set when the timer overflows. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. RW 0 [AES_CTRL:AES_STATUS:AES_STATE:AES_KEY:TRX_STATUS:TRX_STATE:TRX_CTRL_0:TRX_CTRL_1:PHY_TX_PWR:PHY_RSSI:PHY_ED_LEVEL:PHY_CC_CCA:CCA_THRES:RX_CTRL:SFD_VALUE:TRX_CTRL_2:ANT_DIV:IRQ_MASK:IRQ_STATUS:VREG_CTRL:BATMON:XOSC_CTRL:RX_SYN:XAH_CTRL_1:FTN_CTRL:PLL_CF:PLL_DCU:PART_NUM:VERSION_NUM:MAN_ID_0:MAN_ID_1:SHORT_ADDR_0:SHORT_ADDR_1:PAN_ID_0:PAN_ID_1:IEEE_ADDR_0:IEEE_ADDR_1:IEEE_ADDR_2:IEEE_ADDR_3:IEEE_ADDR_4:IEEE_ADDR_5:IEEE_ADDR_6:IEEE_ADDR_7:XAH_CTRL_0:CSMA_SEED_0:CSMA_SEED_1:CSMA_BE:TST_CTRL_DIGI:TST_RX_LENGTH:TRXFBST:TRXFBEND] io_trx24.bmp AES_CTRL AES Control Register This register controls the operation of the security module. Do not access this register during AES operation to read the AES core status. A read or write access to the register stops the ongoing processing. To read the AES status use bit AES_DONE of register AES_STATUS. Note that the AES_CTRL register is cleared when entering the radio transceiver SLEEP state. NA $13C io_flag.bmp Y AES_REQUEST Request AES Operation. A write access with AES_REQUEST = 1 initiates the AES operation. RW 0 Res Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 AES_MODE Set AES Operation Mode This register bit sets the AES operation mode (ECB/CBC Mode). RW 0 AES_MODE_BITF Res Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 AES_DIR Set AES Operation Direction This register bit sets the AES operation direction to either encryption or decryption. RW 0 AES_DIRECTION_BITF AES_IM AES Interrupt Enable This register bit is used to enable the AES interrupt. RW 0 Res1 Reserved Bit These bits are reserved for future use. The result of a read access is undefined. The register bits must always be written with the reset value. R 0 Res0 Reserved Bit These bits are reserved for future use. The result of a read access is undefined. The register bits must always be written with the reset value. R 0 AES_STATUS AES Status Register This read-only register signals the status of the security module and operation. Note that the AES_STATUS register is cleared when entering the radio transceiver SLEEP state. NA $13D io_flag.bmp Y AES_ER AES Operation Finished with Error This register bit indicates an error during AES module run. An error occurs if accessing AES_CTRL while an AES operation is running or if AES_KEY or AES_STATE Memory is not loaded completely or less than 16 Byte read from AES_STATE. R 0 Res5 Reserved These bits are reserved for future use. R 0 Res4 Reserved These bits are reserved for future use. R 0 Res3 Reserved These bits are reserved for future use. R 0 Res2 Reserved These bits are reserved for future use. R 0 Res1 Reserved These bits are reserved for future use. R 0 Res0 Reserved These bits are reserved for future use. R 0 AES_DONE AES Operation Finished with Success This register bit indicates a successfully finished operation of the AES module. R 0 AES_STATE AES Plain and Cipher Text Buffer Register The AES_STATE register accesses a 16 byte internal data buffer. The buffer is accessed by reading or writing 16 times to the same address location (AES_STATE). If the buffer is not completely read or written an error occurs when an AES operation is started. Note that the AES_STATE register is cleared when entering the radio transceiver SLEEP state. NA $13E io_flag.bmp Y AES_STATE7 AES Plain and Cipher Text Buffer These bits represent the data buffer for the AES operation. RW 0 AES_STATE6 AES Plain and Cipher Text Buffer These bits represent the data buffer for the AES operation. RW 0 AES_STATE5 AES Plain and Cipher Text Buffer These bits represent the data buffer for the AES operation. RW 0 AES_STATE4 AES Plain and Cipher Text Buffer These bits represent the data buffer for the AES operation. RW 0 AES_STATE3 AES Plain and Cipher Text Buffer These bits represent the data buffer for the AES operation. RW 0 AES_STATE2 AES Plain and Cipher Text Buffer These bits represent the data buffer for the AES operation. RW 0 AES_STATE1 AES Plain and Cipher Text Buffer These bits represent the data buffer for the AES operation. RW 0 AES_STATE0 AES Plain and Cipher Text Buffer These bits represent the data buffer for the AES operation. RW 0 AES_KEY AES Encryption and Decryption Key Buffer Register The AES key register accesses a 128 Bit internal buffer that holds the Encryption or Decryption Key. The AES_KEY buffer is a 16 Byte buffer. The buffer is accessed by reading or writing 16 fold to the same address location (AES_KEY). A read access to registers AES_KEY returns the last round key of the preceding security operation. This is the key that is required for the corresponding ECB decryption operation after an ECB encryption operation. However, the initial AES key written to the security module in advance of an AES run is not modified during an AES operation. This initial key is used for the next AES run even if it cannot be read from AES_KEY register. Note that the AES_KEY register is cleared when entering the radio transceiver SLEEP state. NA $13F io_flag.bmp Y AES_KEY7 AES Encryption/Decryption Key Buffer These bits represent the data buffer for the AES Encryption/Decryption key. RW 0 AES_KEY6 AES Encryption/Decryption Key Buffer These bits represent the data buffer for the AES Encryption/Decryption key. RW 0 AES_KEY5 AES Encryption/Decryption Key Buffer These bits represent the data buffer for the AES Encryption/Decryption key. RW 0 AES_KEY4 AES Encryption/Decryption Key Buffer These bits represent the data buffer for the AES Encryption/Decryption key. RW 0 AES_KEY3 AES Encryption/Decryption Key Buffer These bits represent the data buffer for the AES Encryption/Decryption key. RW 0 AES_KEY2 AES Encryption/Decryption Key Buffer These bits represent the data buffer for the AES Encryption/Decryption key. RW 0 AES_KEY1 AES Encryption/Decryption Key Buffer These bits represent the data buffer for the AES Encryption/Decryption key. RW 0 AES_KEY0 AES Encryption/Decryption Key Buffer These bits represent the data buffer for the AES Encryption/Decryption key. RW 0 TRX_STATUS Transceiver Status Register This read-only register signals the present state of the radio transceiver as well as the status of the CCA operation. A state change is initiated by writing a state transition command to the TRX_CMD bits of register TRX_STATE. The register is not accessible in SLEEP state. NA $141 io_flag.bmp Y CCA_DONE CCA Algorithm Status This bit indicates if a CCA request is completed. This is also indicated by a TRX24_CCA_ED_DONE interrupt. Note that register bit CCA_DONE is cleared in response to a CCA_REQUEST. R 0 CCA_DONE_bitf CCA_STATUS CCA Status Result The result of the CCA measurement is available in register bit CCA_STATUS after a CCA request is completed. Note that register bit CCA_STATUS is cleared in response to a CCA_REQUEST. R 0 CCA_STATUS_bitf TST_STATUS Test mode status This bit is reserved for internal use. It indicates the status of the test mode. R 0 TST_STATUS_bitf TRX_STATUS4 Transceiver Main Status The register bits TRX_STATUS signal the current radio transceiver status. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. Values not listed in the following table are reserved. R 0 TRX_STATUS3 Transceiver Main Status The register bits TRX_STATUS signal the current radio transceiver status. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. Values not listed in the following table are reserved. R 0 TRX_STATUS2 Transceiver Main Status The register bits TRX_STATUS signal the current radio transceiver status. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. Values not listed in the following table are reserved. R 0 TRX_STATUS1 Transceiver Main Status The register bits TRX_STATUS signal the current radio transceiver status. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. Values not listed in the following table are reserved. R 0 TRX_STATUS0 Transceiver Main Status The register bits TRX_STATUS signal the current radio transceiver status. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. Values not listed in the following table are reserved. R 0 TRX_STATUS_bitf TRX_STATE Transceiver State Control Register The states of the radio transceiver are controlled via register TRX_STATE using register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. A successful state transition shall be confirmed by reading register bits TRX_STATUS. This register is used for both Basic and Extended Operating Mode. NA $142 io_flag.bmp Y TRAC_STATUS2 Transaction Status The status of the RX_AACK and TX_ARET procedure is indicated by register bits TRAC_STATUS. TRAC_STATUS is only valid in Extended Operating Modes. Details of the algorithm and a description of the status information are given in the RX_AACK_ON and TX_ARET_ON sections of the data-sheet. Even though the reset value for register bits TRAC_STATUS is 0, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when it is started. Not all status values are used in both RX_AACK and TX_ARET transactions. In TX_ARET the status SUCCESS_DATA_PENDING indicates a successful reception of an ACK frame with frame pending bit set to 1. In RX_AACK the status SUCCESS_WAIT_FOR_ACK indicates an ACK frame is about to sent in RX_AACK slotted acknowledgment. Slotted acknowledgment operation must be enabled with the SLOTTED_OPERATION bit of register XAH_CTRL_0. The application software must set the SLPTR bit of register TRXPWR at the next back-off slot boundary in order to initiate a transmission of the ACK frame. For details refer to IEEE 802.15.4-2006, chapter 5.5.4.1. Values not listed in the following table are reserved. R 0 TRAC_STATUS1 Transaction Status The status of the RX_AACK and TX_ARET procedure is indicated by register bits TRAC_STATUS. TRAC_STATUS is only valid in Extended Operating Modes. Details of the algorithm and a description of the status information are given in the RX_AACK_ON and TX_ARET_ON sections of the data-sheet. Even though the reset value for register bits TRAC_STATUS is 0, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when it is started. Not all status values are used in both RX_AACK and TX_ARET transactions. In TX_ARET the status SUCCESS_DATA_PENDING indicates a successful reception of an ACK frame with frame pending bit set to 1. In RX_AACK the status SUCCESS_WAIT_FOR_ACK indicates an ACK frame is about to sent in RX_AACK slotted acknowledgment. Slotted acknowledgment operation must be enabled with the SLOTTED_OPERATION bit of register XAH_CTRL_0. The application software must set the SLPTR bit of register TRXPWR at the next back-off slot boundary in order to initiate a transmission of the ACK frame. For details refer to IEEE 802.15.4-2006, chapter 5.5.4.1. Values not listed in the following table are reserved. R 0 TRAC_STATUS0 Transaction Status The status of the RX_AACK and TX_ARET procedure is indicated by register bits TRAC_STATUS. TRAC_STATUS is only valid in Extended Operating Modes. Details of the algorithm and a description of the status information are given in the RX_AACK_ON and TX_ARET_ON sections of the data-sheet. Even though the reset value for register bits TRAC_STATUS is 0, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when it is started. Not all status values are used in both RX_AACK and TX_ARET transactions. In TX_ARET the status SUCCESS_DATA_PENDING indicates a successful reception of an ACK frame with frame pending bit set to 1. In RX_AACK the status SUCCESS_WAIT_FOR_ACK indicates an ACK frame is about to sent in RX_AACK slotted acknowledgment. Slotted acknowledgment operation must be enabled with the SLOTTED_OPERATION bit of register XAH_CTRL_0. The application software must set the SLPTR bit of register TRXPWR at the next back-off slot boundary in order to initiate a transmission of the ACK frame. For details refer to IEEE 802.15.4-2006, chapter 5.5.4.1. Values not listed in the following table are reserved. R 0 TRAC_STATUS_bitf TRX_CMD4 State Control Command A write access to register bits TRX_CMD initiates a state transition of the radio transceiver towards the new state as defined by the write access. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state (see TRX_STATUS register). FORCE_PLL_ON is not valid for the SLEEP state as well as during STATE_TRANSITION_IN_PROGRESS towards the SLEEP state. Values not listed in the following table are reserved and mapped to NOP. RW 0 TRX_CMD3 State Control Command A write access to register bits TRX_CMD initiates a state transition of the radio transceiver towards the new state as defined by the write access. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state (see TRX_STATUS register). FORCE_PLL_ON is not valid for the SLEEP state as well as during STATE_TRANSITION_IN_PROGRESS towards the SLEEP state. Values not listed in the following table are reserved and mapped to NOP. RW 0 TRX_CMD2 State Control Command A write access to register bits TRX_CMD initiates a state transition of the radio transceiver towards the new state as defined by the write access. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state (see TRX_STATUS register). FORCE_PLL_ON is not valid for the SLEEP state as well as during STATE_TRANSITION_IN_PROGRESS towards the SLEEP state. Values not listed in the following table are reserved and mapped to NOP. RW 0 TRX_CMD1 State Control Command A write access to register bits TRX_CMD initiates a state transition of the radio transceiver towards the new state as defined by the write access. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state (see TRX_STATUS register). FORCE_PLL_ON is not valid for the SLEEP state as well as during STATE_TRANSITION_IN_PROGRESS towards the SLEEP state. Values not listed in the following table are reserved and mapped to NOP. RW 0 TRX_CMD0 State Control Command A write access to register bits TRX_CMD initiates a state transition of the radio transceiver towards the new state as defined by the write access. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state (see TRX_STATUS register). FORCE_PLL_ON is not valid for the SLEEP state as well as during STATE_TRANSITION_IN_PROGRESS towards the SLEEP state. Values not listed in the following table are reserved and mapped to NOP. RW 0 TRX_CMD_bitf TRX_CTRL_0 Reserved This register is reserved for future use. NA $143 io_flag.bmp Y Res7 Reserved These bits are reserved for future use. RW 0 Res6 Reserved These bits are reserved for future use. RW 0 Res5 Reserved These bits are reserved for future use. RW 0 Res4 Reserved These bits are reserved for future use. RW 1 Res3 Reserved These bits are reserved for future use. RW 1 Res2 Reserved These bits are reserved for future use. RW 0 Res1 Reserved These bits are reserved for future use. RW 0 Res0 Reserved These bits are reserved for future use. RW 1 TRX_CTRL_1 Transceiver Control Register 1 The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. NA $144 io_flag.bmp Y PA_EXT_EN External PA support enable This register bit enables pin DIG3 and pin DIG4 to indicate the transmit state of the radio transceiver. The control of the external RF front-end is disabled when this bit is 0. Both pins DIG3 and DIG4 are then low. The control of the external front-end is enabled when this bit is 1. DIG3 and DIG4 then indicate the state of the radio transceiver. Pin DIG3 is high and pin DIG4 is low in the state TX_BUSY. In all other states pin DIG3 is low and pin DIG4 is high. It is recommended to set PA_EXT_EN=1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external RF switches or other building blocks especially during SLEEP state. RW 0 IRQ_2_EXT_EN Connect Frame Start IRQ to TC1 When this bit is set to one the capture input of Timer/Counter 1 is connected to the RX frame start signal and pin DIG2 becomes an output, driving the RX frame start signal. Antenna Diversity RF switch control (ANT_EXT_SW_EN=1) shall not be used at the same time, because it shares the same device pin. The function IRQ_2_EXT_EN is available for alternate frame time stamping using Timer/Counter 1. In general the preferred method for frame time stamping is using the symbol counter. RW 0 TX_AUTO_CRC_ON Enable Automatic CRC Calculation This register bit controls the automatic FCS generation for TX operations. The automatic FCS algorithm is performed autonomously by the radio transceiver if register bit TX_AUTO_CRC_ON=1. RW 1 Res4 Reserved R 0 Res3 Reserved R 0 Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 PHY_TX_PWR Transceiver Transmit Power Control Register This register controls the output power and the ramping of the transmitter. NA $145 io_flag.bmp Y PA_BUF_LT1 Power Amplifier Buffer Lead Time These register bits control the enable lead time of the internal PA buffer relative to the enable time of the internal PA. This time is further used to derive a control signal for an external RF front-end to switch between receive and transmit. RW 1 PA_BUF_LT0 Power Amplifier Buffer Lead Time These register bits control the enable lead time of the internal PA buffer relative to the enable time of the internal PA. This time is further used to derive a control signal for an external RF front-end to switch between receive and transmit. RW 1 PA_BUF_LT_bitf PA_LT1 Power Amplifier Lead Time These register bits control the enable lead time of the internal power amplifier relative to the beginning of the transmitted frame (SHR). RW 0 PA_LT0 Power Amplifier Lead Time These register bits control the enable lead time of the internal power amplifier relative to the beginning of the transmitted frame (SHR). RW 0 PA_LT_bitf TX_PWR3 Transmit Power Setting These register bits determine the TX output power of the radio transceiver. RW 0 TX_PWR2 Transmit Power Setting These register bits determine the TX output power of the radio transceiver. RW 0 TX_PWR1 Transmit Power Setting These register bits determine the TX output power of the radio transceiver. RW 0 TX_PWR0 Transmit Power Setting These register bits determine the TX output power of the radio transceiver. RW 0 TX_PWR_bitf PHY_RSSI Receiver Signal Strength Indicator Register The PHY_RSSI register is a multi purpose register that indicates FCS validity, provides random numbers and shows the current RSSI value. NA $146 io_flag.bmp Y RX_CRC_VALID Received Frame CRC Status Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing a TRX24_RX_END interrupt and remains valid until the next TRX24_RX_END interrupt is issued, caused by a new frame reception. R 0 RX_CRC_VALID_bitf RND_VALUE1 Random Value A 2-bit random value can be retrieved by reading register bits RND_VALUE. The value can be used for random numbers for security applications. Note that the radio transceiver shall be in Basic Operating Mode receive state. The values are updated every 1 µs. R 0 RND_VALUE0 Random Value A 2-bit random value can be retrieved by reading register bits RND_VALUE. The value can be used for random numbers for security applications. Note that the radio transceiver shall be in Basic Operating Mode receive state. The values are updated every 1 µs. R 0 RSSI4 Receiver Signal Strength Indicator The result of the automated RSSI measurement is stored in these register bits. The value is updated every 2µs in receive states. The read value is a number between 0 and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale (dBm) with a resolution of 3 dB. A RSSI value of 0 indicates a RF input power lower than RSSI_BASE_VAL (-90 dBm). A value of 28 marks a power higher or equal to -10 dBm. R 0 RSSI3 Receiver Signal Strength Indicator The result of the automated RSSI measurement is stored in these register bits. The value is updated every 2µs in receive states. The read value is a number between 0 and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale (dBm) with a resolution of 3 dB. A RSSI value of 0 indicates a RF input power lower than RSSI_BASE_VAL (-90 dBm). A value of 28 marks a power higher or equal to -10 dBm. R 0 RSSI2 Receiver Signal Strength Indicator The result of the automated RSSI measurement is stored in these register bits. The value is updated every 2µs in receive states. The read value is a number between 0 and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale (dBm) with a resolution of 3 dB. A RSSI value of 0 indicates a RF input power lower than RSSI_BASE_VAL (-90 dBm). A value of 28 marks a power higher or equal to -10 dBm. R 0 RSSI1 Receiver Signal Strength Indicator The result of the automated RSSI measurement is stored in these register bits. The value is updated every 2µs in receive states. The read value is a number between 0 and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale (dBm) with a resolution of 3 dB. A RSSI value of 0 indicates a RF input power lower than RSSI_BASE_VAL (-90 dBm). A value of 28 marks a power higher or equal to -10 dBm. R 0 RSSI0 Receiver Signal Strength Indicator The result of the automated RSSI measurement is stored in these register bits. The value is updated every 2µs in receive states. The read value is a number between 0 and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale (dBm) with a resolution of 3 dB. A RSSI value of 0 indicates a RF input power lower than RSSI_BASE_VAL (-90 dBm). A value of 28 marks a power higher or equal to -10 dBm. R 0 RSSI_VALUE_BITF PHY_ED_LEVEL Transceiver Energy Detection Level Register This register contains the result of an Energy Detection measurement. NA $147 io_flag.bmp Y ED_LEVEL7 Energy Detection Level The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to this register. A value of 0xFF signals that no measurement has yet been started (reset value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 µs. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. R 1 ED_LEVEL6 Energy Detection Level The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to this register. A value of 0xFF signals that no measurement has yet been started (reset value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 µs. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. R 1 ED_LEVEL5 Energy Detection Level The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to this register. A value of 0xFF signals that no measurement has yet been started (reset value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 µs. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. R 1 ED_LEVEL4 Energy Detection Level The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to this register. A value of 0xFF signals that no measurement has yet been started (reset value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 µs. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. R 1 ED_LEVEL3 Energy Detection Level The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to this register. A value of 0xFF signals that no measurement has yet been started (reset value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 µs. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. R 1 ED_LEVEL2 Energy Detection Level The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to this register. A value of 0xFF signals that no measurement has yet been started (reset value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 µs. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. R 1 ED_LEVEL1 Energy Detection Level The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to this register. A value of 0xFF signals that no measurement has yet been started (reset value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 µs. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. R 1 ED_LEVEL0 Energy Detection Level The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to this register. A value of 0xFF signals that no measurement has yet been started (reset value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 µs. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. R 1 ED_LEVEL_BITF PHY_CC_CCA Transceiver Clear Channel Assessment (CCA) Control Register This register is provided to initiate and control a CCA measurement. NA $148 io_flag.bmp Y CCA_REQUEST Manual CCA Measurement Request A manual CCA measurement is initiated with setting CCA_REQUEST=1. The end of the CCA measurement is indicated by the TRX24_CCA_ED_DONE interrupt. Register bits CCA_DONE and CCA_STATUS of register TRX_STATUS are updated after a CCA_REQUEST. The register bit is automatically cleared after requesting a CCA measurement with CCA_REQUEST=1. RW 0 CCA_MODE1 Select CCA Measurement Mode The CCA mode can be selected using these register bits. Note that IEEE 802.15.4-2006 CCA Mode 3 defines the logical combination of CCA Mode 1 and 2 with the logical operators AND or OR. This can be selected with CCA_MODE=0 for logical operation OR and CCA_MODE=3 for logical operation AND. RW 0 CCA_MODE0 Select CCA Measurement Mode The CCA mode can be selected using these register bits. Note that IEEE 802.15.4-2006 CCA Mode 3 defines the logical combination of CCA Mode 1 and 2 with the logical operators AND or OR. This can be selected with CCA_MODE=0 for logical operation OR and CCA_MODE=3 for logical operation AND. RW 1 CCA_MODE_bitf CHANNEL4 RX/TX Channel Selection These register bits define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. RW 0 CHANNEL3 RX/TX Channel Selection These register bits define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. RW 1 CHANNEL2 RX/TX Channel Selection These register bits define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. RW 0 CHANNEL1 RX/TX Channel Selection These register bits define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. RW 1 CHANNEL0 RX/TX Channel Selection These register bits define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. RW 1 CHANNEL_bitf CCA_THRES Transceiver CCA Threshold Setting Register This register sets the threshold level for the Energy Detection (ED) of the Clear Channel Assessment (CCA). NA $149 io_flag.bmp Y CCA_CS_THRES3 CS Threshold Level for CCA Measurement These bits are reserved for internal use. RW 1 CCA_CS_THRES2 CS Threshold Level for CCA Measurement These bits are reserved for internal use. RW 1 CCA_CS_THRES1 CS Threshold Level for CCA Measurement These bits are reserved for internal use. RW 0 CCA_CS_THRES0 CS Threshold Level for CCA Measurement These bits are reserved for internal use. RW 0 CCA_ED_THRES3 ED Threshold Level for CCA Measurement These bits define the received power threshold of the Energy above threshold algorithm. The threshold is calculated by RSSI_BASE_VAL + 2CCA_ED_THRES [dBm]. Any received power above this level is interpreted as a busy channel. RW 0 CCA_ED_THRES2 ED Threshold Level for CCA Measurement These bits define the received power threshold of the Energy above threshold algorithm. The threshold is calculated by RSSI_BASE_VAL + 2CCA_ED_THRES [dBm]. Any received power above this level is interpreted as a busy channel. RW 1 CCA_ED_THRES1 ED Threshold Level for CCA Measurement These bits define the received power threshold of the Energy above threshold algorithm. The threshold is calculated by RSSI_BASE_VAL + 2CCA_ED_THRES [dBm]. Any received power above this level is interpreted as a busy channel. RW 1 CCA_ED_THRES0 ED Threshold Level for CCA Measurement These bits define the received power threshold of the Energy above threshold algorithm. The threshold is calculated by RSSI_BASE_VAL + 2CCA_ED_THRES [dBm]. Any received power above this level is interpreted as a busy channel. RW 1 RX_CTRL Transceiver Receive Control Register The register controls the sensitivity of the Antenna Diversity Mode. Note that in High Data Rate modes the ACR module will always be disabled. NA $14A io_flag.bmp Y PDT_THRES3 Receiver Sensitivity Control These register bits control the sensitivity of the receiver correlation unit. If the Antenna Diversity algorithm is enabled the value shall be set to PDT_THRES = 3. Otherwise it shall be set back to the reset value. Values not listed in the following table are reserved. RW 0 PDT_THRES2 Receiver Sensitivity Control These register bits control the sensitivity of the receiver correlation unit. If the Antenna Diversity algorithm is enabled the value shall be set to PDT_THRES = 3. Otherwise it shall be set back to the reset value. Values not listed in the following table are reserved. RW 1 PDT_THRES1 Receiver Sensitivity Control These register bits control the sensitivity of the receiver correlation unit. If the Antenna Diversity algorithm is enabled the value shall be set to PDT_THRES = 3. Otherwise it shall be set back to the reset value. Values not listed in the following table are reserved. RW 1 PDT_THRES0 Receiver Sensitivity Control These register bits control the sensitivity of the receiver correlation unit. If the Antenna Diversity algorithm is enabled the value shall be set to PDT_THRES = 3. Otherwise it shall be set back to the reset value. Values not listed in the following table are reserved. RW 1 PDT_THRES_bitf SFD_VALUE Start of Frame Delimiter Value Register This register contains the one octet start-of-frame delimiter (SFD) to synchronize to a received frame. The lower 4 bits must not be all zero to avoid decoding conflicts. NA $14B io_flag.bmp Y SFD_VALUE7 Start of Frame Delimiter Value For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled a RX_START interrupt is issued only if the received SFD matches the register content of SFD_VALUE and a valid PHR is received. RW 1 SFD_VALUE6 Start of Frame Delimiter Value For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled a RX_START interrupt is issued only if the received SFD matches the register content of SFD_VALUE and a valid PHR is received. RW 0 SFD_VALUE5 Start of Frame Delimiter Value For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled a RX_START interrupt is issued only if the received SFD matches the register content of SFD_VALUE and a valid PHR is received. RW 1 SFD_VALUE4 Start of Frame Delimiter Value For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled a RX_START interrupt is issued only if the received SFD matches the register content of SFD_VALUE and a valid PHR is received. RW 0 SFD_VALUE3 Start of Frame Delimiter Value For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled a RX_START interrupt is issued only if the received SFD matches the register content of SFD_VALUE and a valid PHR is received. RW 0 SFD_VALUE2 Start of Frame Delimiter Value For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled a RX_START interrupt is issued only if the received SFD matches the register content of SFD_VALUE and a valid PHR is received. RW 1 SFD_VALUE1 Start of Frame Delimiter Value For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled a RX_START interrupt is issued only if the received SFD matches the register content of SFD_VALUE and a valid PHR is received. RW 1 SFD_VALUE0 Start of Frame Delimiter Value For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled a RX_START interrupt is issued only if the received SFD matches the register content of SFD_VALUE and a valid PHR is received. RW 1 SFD_VALUE_BITF TRX_CTRL_2 Transceiver Control Register 2 This register controls the data rate setting of the radio transceiver. NA $14C io_flag.bmp Y RX_SAFE_MODE RX Safe Mode If this bit is set, the next received frame will be protected and not overwritten by following frames. Set this bit to 0 to release the buffer (and set it again for further protection). RW 0 Res4 Reserved R 0 Res3 Reserved R 0 Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 OQPSK_DATA_RATE1 Data Rate Selection A write access to these register bits sets the OQPSK PSDU data rate used by the radio transceiver. The reset value OQPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE 802.15.4. All other values are used in High Data Rate Modes. RW 0 OQPSK_DATA_RATE0 Data Rate Selection A write access to these register bits sets the OQPSK PSDU data rate used by the radio transceiver. The reset value OQPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE 802.15.4. All other values are used in High Data Rate Modes. RW 0 OQPSK_DATA_RATE_bitf ANT_DIV Antenna Diversity Control Register This register controls the Antenna Diversity. NA $14D io_flag.bmp Y ANT_SEL Antenna Diversity Antenna Status This register bit signals the currently selected antenna path. The selection may be based either on the last antenna diversity cycle (ANT_DIV_EN = 1) or on the content of register bits ANT_CTRL. R 0 ANT_SEL_bitf Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 ANT_DIV_EN Enable Antenna Diversity If this register bit is set the Antenna Diversity algorithm is enabled. On reception of a frame the algorithm selects an antenna autonomously during SHR search. This selection is kept until 1. a new SHR search starts or 2. receive states are left or 3. a manually programming of bits ANT_CTRL occurred. If ANT_DIV_EN = 1 the bit ANT_EXT_SW_EN shall also be set to 1. RW 0 ANT_DIV_EN_bitf ANT_EXT_SW_EN Enable External Antenna Switch Control If enabled, pin DIG1 and pin DIG2 become output pins and provide a differential control signal for an external Antenna Diversity switch. The selection of a specific antenna is done either by the automatic Antenna Diversity algorithm (ANT_DIV_EN = 1) or according to bits ANT_CTRL if the Antenna Diversity algorithm is disabled. Do not enable Antenna Diversity RF switch control (ANT_EXT_SW_EN = 1) and RX Frame Time Stamping (IRQ_2_EXT_EN = 1, see register TRX_CTRL_1) at the same time. If this bit is set the control pins DIG1/DIG2 are activated in all radio transceiver states as long as bit ANT_EXT_SW_EN is also set. If the radio transceiver is not in a receive or transmit state, it is recommended to disable bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch especially during SLEEP state. The output pins DIG1 and DIG2 are pulled-down to digital ground if bit ANT_EXT_SW_EN = 0. RW 0 ANT_EXT_SW_EN_bitf ANT_CTRL1 Static Antenna Diversity Switch Control These bits provide a static control of an Antenna Diversity switch. This register setting defines the selected antenna if ANT_DIV_EN is set to 0 (Antenna Diversity disabled). Register values 1 and 2 are valid for ANT_EXT_SW_EN = 1. RW 1 ANT_CTRL0 Static Antenna Diversity Switch Control These bits provide a static control of an Antenna Diversity switch. This register setting defines the selected antenna if ANT_DIV_EN is set to 0 (Antenna Diversity disabled). Register values 1 and 2 are valid for ANT_EXT_SW_EN = 1. RW 1 ANT_CTRL_bitf IRQ_MASK Transceiver Interrupt Enable Register This register is used to enable or disable individual interrupts of the radio transceiver. An interrupt is enabled if the corresponding bit is set to 1. All interrupts are disabled after the power up sequence or reset. If an interrupt is enabled it is recommended to read the interrupt status register IRQ_STATUS first to clear the history. NA $14E io_flag.bmp Y AWAKE_EN Awake Interrupt Enable RW 0 TX_END_EN TX_END Interrupt Enable RW 0 AMI_EN Address Match Interrupt Enable RW 0 CCA_ED_DONE_EN End of ED Measurement Interrupt Enable RW 0 RX_END_EN RX_END Interrupt Enable RW 0 RX_START_EN RX_START Interrupt Enable RW 0 PLL_UNLOCK_EN PLL Unlock Interrupt Enable RW 0 PLL_LOCK_EN PLL Lock Interrupt Enable RW 0 IRQ_STATUS Transceiver Interrupt Status Register This register contains the status of the pending interrupt requests. An interrupt is pending if the associated bit has a value of one. Such a pending interrupts can be manually cleared by writing a 1 to that register bit. Interrupts are automatically cleared when the corresponding interrupt service routine is being executed. NA $14F io_flag.bmp Y AWAKE Awake Interrupt Status RW 0 TX_END TX_END Interrupt Status RW 0 AMI Address Match Interrupt Status RW 0 CCA_ED_DONE End of ED Measurement Interrupt Status RW 0 RX_END RX_END Interrupt Status RW 0 RX_START RX_START Interrupt Status RW 0 PLL_UNLOCK PLL Unlock Interrupt Status RW 0 PLL_LOCK PLL Lock Interrupt Status RW 0 VREG_CTRL Voltage Regulator Control and Status Register This register controls the use of the voltage regulators and indicates their status. NA $150 io_flag.bmp Y AVREG_EXT Use External AVDD Regulator If set, this register bit disables the internal analog voltage regulator to apply an external regulated 1.8V supply for the analog building blocks. RW 0 AVREG_EXT_BITF AVDD_OK AVDD Supply Voltage Valid This register bit indicates if the internal 1.8V regulated voltage supply AVDD has settled. The bit is set to logic high if AVREG_EXT = 1. R 0 AVDD_OK_BITF DVREG_EXT Use External DVDD Regulator If set this register bit disables the internal digital voltage regulator to apply an external regulated 1.8V supply for the digital building blocks. RW 0 DVREG_EXT_BITF DVDD_OK DVDD Supply Voltage Valid This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high if DVREG_EXT = 1. R 0 DVDD_OK_BITF BATMON Battery Monitor Control and Status Register This register configures the battery monitor to observe the supply voltage at EVDD. The status of the EVDD supply voltage is accessible by reading bit BATMON_OK with respect to the actual BATMON settings. Furthermore the Battery Monitor Interrupt can be controlled with the bits BAT_LOW and BAT_LOW_EN similar to the function of the IRQ_STATUS and IRQ_MASK register for other radio transceiver interrupts. NA $151 io_flag.bmp Y BAT_LOW Battery Monitor Interrupt Status A BATMON Interrupt is pending if this bit is set. Writing one to this bit if it has been at one will clear the interrupt. RW 0 BAT_LOW_EN Battery Monitor Interrupt Enable The Battery Monitor Interrupt is enabled if this bit is set to one. The Battery Monitor will not generate an interrupt if this bit is zero. RW 0 BATMON_OK Battery Monitor Status The register bit BATMON_OK indicates the level of the external supply voltage with respect to the programmed threshold BATMON_VTH. R 0 BATMON_OK_bitf BATMON_HR Battery Monitor Voltage Range This bit sets the range and resolution of the battery monitor. RW 0 BATMON_HR_bitf BATMON_VTH3 Battery Monitor Threshold Voltage The threshold values for the battery monitor are set by these register bits according to the following table. RW 0 BATMON_VTH2 Battery Monitor Threshold Voltage The threshold values for the battery monitor are set by these register bits according to the following table. RW 0 BATMON_VTH1 Battery Monitor Threshold Voltage The threshold values for the battery monitor are set by these register bits according to the following table. RW 1 BATMON_VTH0 Battery Monitor Threshold Voltage The threshold values for the battery monitor are set by these register bits according to the following table. RW 0 BATMON_VTH_bitf XOSC_CTRL Crystal Oscillator Control Register This register controls the operation of the 16MHz crystal oscillator. NA $152 io_flag.bmp Y XTAL_MODE3 Crystal Oscillator Operating Mode These register bits set the operating mode of the 16 MHz crystal oscillator. For normal operation the default value is set to XTAL_MODE = 0xF after reset. For use with an external clock source it is recommended to set XTAL_MODE = 0x4. RW 1 XTAL_MODE2 Crystal Oscillator Operating Mode These register bits set the operating mode of the 16 MHz crystal oscillator. For normal operation the default value is set to XTAL_MODE = 0xF after reset. For use with an external clock source it is recommended to set XTAL_MODE = 0x4. RW 1 XTAL_MODE1 Crystal Oscillator Operating Mode These register bits set the operating mode of the 16 MHz crystal oscillator. For normal operation the default value is set to XTAL_MODE = 0xF after reset. For use with an external clock source it is recommended to set XTAL_MODE = 0x4. RW 1 XTAL_MODE0 Crystal Oscillator Operating Mode These register bits set the operating mode of the 16 MHz crystal oscillator. For normal operation the default value is set to XTAL_MODE = 0xF after reset. For use with an external clock source it is recommended to set XTAL_MODE = 0x4. RW 1 XTAL_MODE_BITF XTAL_TRIM3 Crystal Oscillator Load Capacitance Trimming These register bits control two internal capacitance arrays connected to pins XTAL1 and XTAL2. A capacitance value in the range from 0 pF to 4.5 pF is selectable with a resolution of 0.3 pF. RW 0 XTAL_TRIM2 Crystal Oscillator Load Capacitance Trimming These register bits control two internal capacitance arrays connected to pins XTAL1 and XTAL2. A capacitance value in the range from 0 pF to 4.5 pF is selectable with a resolution of 0.3 pF. RW 0 XTAL_TRIM1 Crystal Oscillator Load Capacitance Trimming These register bits control two internal capacitance arrays connected to pins XTAL1 and XTAL2. A capacitance value in the range from 0 pF to 4.5 pF is selectable with a resolution of 0.3 pF. RW 0 XTAL_TRIM0 Crystal Oscillator Load Capacitance Trimming These register bits control two internal capacitance arrays connected to pins XTAL1 and XTAL2. A capacitance value in the range from 0 pF to 4.5 pF is selectable with a resolution of 0.3 pF. RW 0 XTAL_TRIM_bitf RX_SYN Transceiver Receiver Sensitivity Control Register This register controls the sensitivity threshold of the receiver. NA $155 io_flag.bmp Y RX_PDT_DIS Prevent Frame Reception RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive modes. An ongoing frame reception is not affected. This operation mode is independent of the setting of register bits RX_PDT_LEVEL. RW 0 Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 RX_PDT_LEVEL3 Reduce Receiver Sensitivity These register bits reduce the receiver sensitivity such that frames with a RSSI level below the RX_PDT_LEVEL threshold level are not received (RX_PDT_LEVEL>0). The threshold level can be calculated according to the following formula: RX_THRES > RSSI_BASE_VAL+3·(RX_PDT_LEVEL-1), for RX_PDT_LEVEL>0. If register bits RX_PDT_LEVEL>0 the current consumption of the receiver in states RX_ON and RX_AACK_ON is reduced by 500 µA. If register bits RX_PDT_LEVEL=0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength. Examples for certain register settings are given in the following table. RW 0 RX_PDT_LEVEL2 Reduce Receiver Sensitivity These register bits reduce the receiver sensitivity such that frames with a RSSI level below the RX_PDT_LEVEL threshold level are not received (RX_PDT_LEVEL>0). The threshold level can be calculated according to the following formula: RX_THRES > RSSI_BASE_VAL+3·(RX_PDT_LEVEL-1), for RX_PDT_LEVEL>0. If register bits RX_PDT_LEVEL>0 the current consumption of the receiver in states RX_ON and RX_AACK_ON is reduced by 500 µA. If register bits RX_PDT_LEVEL=0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength. Examples for certain register settings are given in the following table. RW 0 RX_PDT_LEVEL1 Reduce Receiver Sensitivity These register bits reduce the receiver sensitivity such that frames with a RSSI level below the RX_PDT_LEVEL threshold level are not received (RX_PDT_LEVEL>0). The threshold level can be calculated according to the following formula: RX_THRES > RSSI_BASE_VAL+3·(RX_PDT_LEVEL-1), for RX_PDT_LEVEL>0. If register bits RX_PDT_LEVEL>0 the current consumption of the receiver in states RX_ON and RX_AACK_ON is reduced by 500 µA. If register bits RX_PDT_LEVEL=0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength. Examples for certain register settings are given in the following table. RW 0 RX_PDT_LEVEL0 Reduce Receiver Sensitivity These register bits reduce the receiver sensitivity such that frames with a RSSI level below the RX_PDT_LEVEL threshold level are not received (RX_PDT_LEVEL>0). The threshold level can be calculated according to the following formula: RX_THRES > RSSI_BASE_VAL+3·(RX_PDT_LEVEL-1), for RX_PDT_LEVEL>0. If register bits RX_PDT_LEVEL>0 the current consumption of the receiver in states RX_ON and RX_AACK_ON is reduced by 500 µA. If register bits RX_PDT_LEVEL=0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength. Examples for certain register settings are given in the following table. RW 0 RX_PDT_LEVEL_BITF XAH_CTRL_1 Transceiver Acknowledgment Frame Control Register 1 This register is a multi-purpose control register for various RX_AACK settings. NA $157 io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res0 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 AACK_FLTR_RES_FT Filter Reserved Frames This register bit shall only be set if AACK_UPLD_RES_FT = 1. If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4 section 7.2.1.1.1. If AACK_FLTR_RES_FT = 0 a received, reserved frame is only checked for a valid FCS. RW 0 AACK_UPLD_RES_FT Process Reserved Frames If AACK_UPLD_RES_FT = 1 received frames indicated as reserved are further processed. A RX_END interrupt is generated if the FCS of those frames is valid. In conjunction with the configuration bit AACK_FLTR_RES_FT set, these frames are handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction. An AMI interrupt is issued if the address in the received frame matches the node address. That means if a reserved frame passes the third level filter rules, an acknowledgment frame is generated and transmitted if it was requested by the received frame. If this is not wanted bit AACK_DIS_ACK in register CSMA_SEED_1 has to be set. RW 0 Res Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 AACK_ACK_TIME Reduce Acknowledgment Time According to IEEE 802.15.4, section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbols (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is achieved with the reset value of the register bit AACK_ACK_TIME. If AACK_ACK_TIME = 1 an acknowledgment frame is alternatively sent already 2 symbol periods (32 µs) after the reception of the last symbol of a data or MAC command frame. This may be applied to proprietary networks or networks using the High Data Rate Modes to increase battery lifetime and to improve the overall data throughput. This setting affects also to acknowledgment frame response time for slotted acknowledgment operation. RW 0 AACK_ACK_TIME_bitf AACK_PROM_MODE Enable Promiscuous Mode This register bit enables the promiscuous mode within the RX_AACK mode; refer to IEEE 802.15.4-2006 chapter 7.5.6.5. If this bit is set, every incoming frame with a valid PHR finishes with a RX_END interrupt even if the third level filter rules do not match or the FCS is not valid. The bit RX_CRC_VALID of register PHY_RSSI is set accordingly. If this bit is set and a frame passes the third level filter rules, an acknowledgment frame is generated and transmitted unless disabled by bit AACK_DIS_ACK of register CSMA_SEED_1. RW 0 Res Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 FTN_CTRL Transceiver Filter Tuning Control Register This register controls the operation of the calibration loop of the filter tuning network. NA $158 io_flag.bmp Y FTN_START Start Calibration Loop of Filter Tuning Network FTN_START = 1 initiates the calibration of the filter tuning network. When the calibration cycle has finished after at most 25 µs the register bit is automatically reset to 0. RW 0 PLL_CF Transceiver Center Frequency Calibration Control Register This register controls the operation of the center frequency calibration loop. NA $15A io_flag.bmp Y PLL_CF_START Start Center Frequency Calibration PLL_CF_START = 1 initiates the center frequency calibration. The calibration cycle has finished after 35 µs (typical). The register bit is cleared immediately after finishing the calibration. RW 0 PLL_DCU Transceiver Delay Cell Calibration Control Register This register controls the operation of the calibration loop of the delay cell. NA $15B io_flag.bmp Y PLL_DCU_START Start Delay Cell Calibration PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after at most 6 µs. The register bit is cleared immediately after finishing the calibration. RW 0 PART_NUM Device Identification Register (Part Number) This register contains the part number of the device. NA $15C io_flag.bmp Y PART_NUM7 Part Number These bits decode the part number of the device according to the following table. R 1 PART_NUM6 Part Number These bits decode the part number of the device according to the following table. R 0 PART_NUM5 Part Number These bits decode the part number of the device according to the following table. R 0 PART_NUM4 Part Number These bits decode the part number of the device according to the following table. R 0 PART_NUM3 Part Number These bits decode the part number of the device according to the following table. R 0 PART_NUM2 Part Number These bits decode the part number of the device according to the following table. R 0 PART_NUM1 Part Number These bits decode the part number of the device according to the following table. R 1 PART_NUM0 Part Number These bits decode the part number of the device according to the following table. R 1 PART_NUM_bitf VERSION_NUM Device Identification Register (Version Number) This register contains the version number of the device. NA $15D io_flag.bmp Y VERSION_NUM7 Version Number These bits decode the version number of the device according to the following table. R 0 VERSION_NUM6 Version Number These bits decode the version number of the device according to the following table. R 0 VERSION_NUM5 Version Number These bits decode the version number of the device according to the following table. R 0 VERSION_NUM4 Version Number These bits decode the version number of the device according to the following table. R 0 VERSION_NUM3 Version Number These bits decode the version number of the device according to the following table. R 0 VERSION_NUM2 Version Number These bits decode the version number of the device according to the following table. R 0 VERSION_NUM1 Version Number These bits decode the version number of the device according to the following table. R 1 VERSION_NUM0 Version Number These bits decode the version number of the device according to the following table. R 1 VERSION_NUM_BITF MAN_ID_0 Device Identification Register (Manufacture ID Low Byte) Bits [7:0] of the 32-bit JEDEC manufacturer ID are stored in this register. Bits [15:8] are stored in register MAN_ID_1. The highest 16 bits of the JEDEC ID are not stored in registers. NA $15E io_flag.bmp Y MAN_ID_07 Manufacturer ID (Low Byte) These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_06 Manufacturer ID (Low Byte) These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_05 Manufacturer ID (Low Byte) These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_04 Manufacturer ID (Low Byte) These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID. R 1 MAN_ID_03 Manufacturer ID (Low Byte) These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID. R 1 MAN_ID_02 Manufacturer ID (Low Byte) These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID. R 1 MAN_ID_01 Manufacturer ID (Low Byte) These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID. R 1 MAN_ID_00 Manufacturer ID (Low Byte) These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID. R 1 MAN_ID_0_BITF MAN_ID_1 Device Identification Register (Manufacture ID High Byte) Bits [15:8] of the 32-bit JEDEC manufacturer ID are stored in this register. Bits [7:0] are stored in register MAN_ID_0. The highest 16 bits of the JEDEC ID are not stored in registers. NA $15F io_flag.bmp Y MAN_ID_17 Manufacturer ID (High Byte) These bits contain bits [15:8] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_16 Manufacturer ID (High Byte) These bits contain bits [15:8] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_15 Manufacturer ID (High Byte) These bits contain bits [15:8] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_14 Manufacturer ID (High Byte) These bits contain bits [15:8] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_13 Manufacturer ID (High Byte) These bits contain bits [15:8] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_12 Manufacturer ID (High Byte) These bits contain bits [15:8] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_11 Manufacturer ID (High Byte) These bits contain bits [15:8] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_10 Manufacturer ID (High Byte) These bits contain bits [15:8] of the 32-bit JEDEC manufacturer ID. R 0 MAN_ID_1_BITF SHORT_ADDR_0 Transceiver MAC Short Address Register (Low Byte) This register contains the lower 8 bits of the MAC short address for Frame Filter address recognition. NA $160 io_flag.bmp Y SHORT_ADDR_07 MAC Short Address These bits contain the bits [7:0] of the MAC short address. RW 1 SHORT_ADDR_06 MAC Short Address These bits contain the bits [7:0] of the MAC short address. RW 1 SHORT_ADDR_05 MAC Short Address These bits contain the bits [7:0] of the MAC short address. RW 1 SHORT_ADDR_04 MAC Short Address These bits contain the bits [7:0] of the MAC short address. RW 1 SHORT_ADDR_03 MAC Short Address These bits contain the bits [7:0] of the MAC short address. RW 1 SHORT_ADDR_02 MAC Short Address These bits contain the bits [7:0] of the MAC short address. RW 1 SHORT_ADDR_01 MAC Short Address These bits contain the bits [7:0] of the MAC short address. RW 1 SHORT_ADDR_00 MAC Short Address These bits contain the bits [7:0] of the MAC short address. RW 1 SHORT_ADDR_1 Transceiver MAC Short Address Register (High Byte) This register contains the upper 8 bits of the MAC short address for Frame Filter address recognition. NA $161 io_flag.bmp Y SHORT_ADDR_17 MAC Short Address These bits contain the bits [15:8] of the MAC short address. RW 1 SHORT_ADDR_16 MAC Short Address These bits contain the bits [15:8] of the MAC short address. RW 1 SHORT_ADDR_15 MAC Short Address These bits contain the bits [15:8] of the MAC short address. RW 1 SHORT_ADDR_14 MAC Short Address These bits contain the bits [15:8] of the MAC short address. RW 1 SHORT_ADDR_13 MAC Short Address These bits contain the bits [15:8] of the MAC short address. RW 1 SHORT_ADDR_12 MAC Short Address These bits contain the bits [15:8] of the MAC short address. RW 1 SHORT_ADDR_11 MAC Short Address These bits contain the bits [15:8] of the MAC short address. RW 1 SHORT_ADDR_10 MAC Short Address These bits contain the bits [15:8] of the MAC short address. RW 1 PAN_ID_0 Transceiver Personal Area Network ID Register (Low Byte) This register contains the lower 8 bits of the MAC PAN ID for Frame Filter address recognition. NA $162 io_flag.bmp Y PAN_ID_07 MAC Personal Area Network ID These bits contain the bits [7:0] of the MAC PAN ID. RW 1 PAN_ID_06 MAC Personal Area Network ID These bits contain the bits [7:0] of the MAC PAN ID. RW 1 PAN_ID_05 MAC Personal Area Network ID These bits contain the bits [7:0] of the MAC PAN ID. RW 1 PAN_ID_04 MAC Personal Area Network ID These bits contain the bits [7:0] of the MAC PAN ID. RW 1 PAN_ID_03 MAC Personal Area Network ID These bits contain the bits [7:0] of the MAC PAN ID. RW 1 PAN_ID_02 MAC Personal Area Network ID These bits contain the bits [7:0] of the MAC PAN ID. RW 1 PAN_ID_01 MAC Personal Area Network ID These bits contain the bits [7:0] of the MAC PAN ID. RW 1 PAN_ID_00 MAC Personal Area Network ID These bits contain the bits [7:0] of the MAC PAN ID. RW 1 PAN_ID_1 Transceiver Personal Area Network ID Register (High Byte) This register contains the upper 8 bits of the MAC PAN ID for Frame Filter address recognition. NA $163 io_flag.bmp Y PAN_ID_17 MAC Personal Area Network ID These bits contain the bits [15:8] of the MAC PAN ID. RW 1 PAN_ID_16 MAC Personal Area Network ID These bits contain the bits [15:8] of the MAC PAN ID. RW 1 PAN_ID_15 MAC Personal Area Network ID These bits contain the bits [15:8] of the MAC PAN ID. RW 1 PAN_ID_14 MAC Personal Area Network ID These bits contain the bits [15:8] of the MAC PAN ID. RW 1 PAN_ID_13 MAC Personal Area Network ID These bits contain the bits [15:8] of the MAC PAN ID. RW 1 PAN_ID_12 MAC Personal Area Network ID These bits contain the bits [15:8] of the MAC PAN ID. RW 1 PAN_ID_11 MAC Personal Area Network ID These bits contain the bits [15:8] of the MAC PAN ID. RW 1 PAN_ID_10 MAC Personal Area Network ID These bits contain the bits [15:8] of the MAC PAN ID. RW 1 IEEE_ADDR_0 Transceiver MAC IEEE Address Register 0 This register contains the bits [7:0] of the MAC IEEE address for Frame Filter address recognition. NA $164 io_flag.bmp Y IEEE_ADDR_07 MAC IEEE Address These bits map to the bits [7:0] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_06 MAC IEEE Address These bits map to the bits [7:0] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_05 MAC IEEE Address These bits map to the bits [7:0] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_04 MAC IEEE Address These bits map to the bits [7:0] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_03 MAC IEEE Address These bits map to the bits [7:0] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_02 MAC IEEE Address These bits map to the bits [7:0] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_01 MAC IEEE Address These bits map to the bits [7:0] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_00 MAC IEEE Address These bits map to the bits [7:0] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_1 Transceiver MAC IEEE Address Register 1 This register contains the bits [15:8] of the MAC IEEE address for Frame Filter address recognition. NA $165 io_flag.bmp Y IEEE_ADDR_17 MAC IEEE Address These bits map to the bits [15:8] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_16 MAC IEEE Address These bits map to the bits [15:8] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_15 MAC IEEE Address These bits map to the bits [15:8] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_14 MAC IEEE Address These bits map to the bits [15:8] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_13 MAC IEEE Address These bits map to the bits [15:8] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_12 MAC IEEE Address These bits map to the bits [15:8] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_11 MAC IEEE Address These bits map to the bits [15:8] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_10 MAC IEEE Address These bits map to the bits [15:8] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_2 Transceiver MAC IEEE Address Register 2 This register contains the bits [23:16] of the MAC IEEE address for Frame Filter address recognition. NA $166 io_flag.bmp Y IEEE_ADDR_27 MAC IEEE Address These bits map to the bits [23:16] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_26 MAC IEEE Address These bits map to the bits [23:16] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_25 MAC IEEE Address These bits map to the bits [23:16] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_24 MAC IEEE Address These bits map to the bits [23:16] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_23 MAC IEEE Address These bits map to the bits [23:16] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_22 MAC IEEE Address These bits map to the bits [23:16] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_21 MAC IEEE Address These bits map to the bits [23:16] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_20 MAC IEEE Address These bits map to the bits [23:16] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_3 Transceiver MAC IEEE Address Register 3 This register contains the bits [31:24] of the MAC IEEE address for Frame Filter address recognition. NA $167 io_flag.bmp Y IEEE_ADDR_37 MAC IEEE Address These bits map to the bits [31:24] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_36 MAC IEEE Address These bits map to the bits [31:24] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_35 MAC IEEE Address These bits map to the bits [31:24] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_34 MAC IEEE Address These bits map to the bits [31:24] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_33 MAC IEEE Address These bits map to the bits [31:24] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_32 MAC IEEE Address These bits map to the bits [31:24] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_31 MAC IEEE Address These bits map to the bits [31:24] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_30 MAC IEEE Address These bits map to the bits [31:24] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_4 Transceiver MAC IEEE Address Register 4 This register contains the bits [39:32] of the MAC IEEE address for Frame Filter address recognition. NA $168 io_flag.bmp Y IEEE_ADDR_47 MAC IEEE Address These bits map to the bits [39:32] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_46 MAC IEEE Address These bits map to the bits [39:32] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_45 MAC IEEE Address These bits map to the bits [39:32] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_44 MAC IEEE Address These bits map to the bits [39:32] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_43 MAC IEEE Address These bits map to the bits [39:32] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_42 MAC IEEE Address These bits map to the bits [39:32] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_41 MAC IEEE Address These bits map to the bits [39:32] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_40 MAC IEEE Address These bits map to the bits [39:32] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_5 Transceiver MAC IEEE Address Register 5 This register contains the bits [47:40] of the MAC IEEE address for Frame Filter address recognition. NA $169 io_flag.bmp Y IEEE_ADDR_57 MAC IEEE Address These bits map to the bits [47:40] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_56 MAC IEEE Address These bits map to the bits [47:40] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_55 MAC IEEE Address These bits map to the bits [47:40] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_54 MAC IEEE Address These bits map to the bits [47:40] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_53 MAC IEEE Address These bits map to the bits [47:40] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_52 MAC IEEE Address These bits map to the bits [47:40] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_51 MAC IEEE Address These bits map to the bits [47:40] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_50 MAC IEEE Address These bits map to the bits [47:40] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_6 Transceiver MAC IEEE Address Register 6 This register contains the bits [55:48] of the MAC IEEE address for Frame Filter address recognition. NA $16A io_flag.bmp Y IEEE_ADDR_67 MAC IEEE Address These bits map to the bits [55:48] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_66 MAC IEEE Address These bits map to the bits [55:48] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_65 MAC IEEE Address These bits map to the bits [55:48] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_64 MAC IEEE Address These bits map to the bits [55:48] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_63 MAC IEEE Address These bits map to the bits [55:48] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_62 MAC IEEE Address These bits map to the bits [55:48] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_61 MAC IEEE Address These bits map to the bits [55:48] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_60 MAC IEEE Address These bits map to the bits [55:48] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_7 Transceiver MAC IEEE Address Register 7 This register contains the bits [63:56] of the MAC IEEE address for Frame Filter address recognition. NA $16B io_flag.bmp Y IEEE_ADDR_77 MAC IEEE Address These bits map to the bits [63:56] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_76 MAC IEEE Address These bits map to the bits [63:56] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_75 MAC IEEE Address These bits map to the bits [63:56] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_74 MAC IEEE Address These bits map to the bits [63:56] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_73 MAC IEEE Address These bits map to the bits [63:56] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_72 MAC IEEE Address These bits map to the bits [63:56] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_71 MAC IEEE Address These bits map to the bits [63:56] of the 64 bit MAC IEEE address. RW 0 IEEE_ADDR_70 MAC IEEE Address These bits map to the bits [63:56] of the 64 bit MAC IEEE address. RW 0 XAH_CTRL_0 Transceiver Extended Operating Mode Control Register This register is used to control various settings of the Extended Operating Mode. NA $16C io_flag.bmp Y MAX_FRAME_RETRIES3 Maximum Number of Frame Re-transmission Attempts The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a frame when it was not acknowledged by the recipient. The transaction gets canceled if the number of attempts exceeds MAX_FRAME_RETRIES. RW 0 MAX_FRAME_RETRIES2 Maximum Number of Frame Re-transmission Attempts The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a frame when it was not acknowledged by the recipient. The transaction gets canceled if the number of attempts exceeds MAX_FRAME_RETRIES. RW 0 MAX_FRAME_RETRIES1 Maximum Number of Frame Re-transmission Attempts The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a frame when it was not acknowledged by the recipient. The transaction gets canceled if the number of attempts exceeds MAX_FRAME_RETRIES. RW 1 MAX_FRAME_RETRIES0 Maximum Number of Frame Re-transmission Attempts The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a frame when it was not acknowledged by the recipient. The transaction gets canceled if the number of attempts exceeds MAX_FRAME_RETRIES. RW 1 MAX_FRAME_RETRIES_bitf MAX_CSMA_RETRIES2 Maximum Number of CSMA-CA Procedure Repetition Attempts MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets canceled. According to IEEE 802.15.4 the valid range of MAX_CSMA_RETRIES is 0 to 5. A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without performing CSMA-CA. This may especially be required for slotted acknowledgment operation. MAX_CSMA_RETRIES = 6 is reserved. RW 1 MAX_CSMA_RETRIES1 Maximum Number of CSMA-CA Procedure Repetition Attempts MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets canceled. According to IEEE 802.15.4 the valid range of MAX_CSMA_RETRIES is 0 to 5. A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without performing CSMA-CA. This may especially be required for slotted acknowledgment operation. MAX_CSMA_RETRIES = 6 is reserved. RW 0 MAX_CSMA_RETRIES0 Maximum Number of CSMA-CA Procedure Repetition Attempts MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets canceled. According to IEEE 802.15.4 the valid range of MAX_CSMA_RETRIES is 0 to 5. A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without performing CSMA-CA. This may especially be required for slotted acknowledgment operation. MAX_CSMA_RETRIES = 6 is reserved. RW 0 MAX_CSMA_RETRIES_bitf SLOTTED_OPERATION Set Slotted Acknowledgment When using RX_AACK mode in networks operating in beacon or slotted mode according to IEEE 802.15.4-2006, chapter 5.5.1 the register bit SLOTTED_OPERATION indicates that acknowledgment frames are to be sent on back-off slot boundaries (slotted acknowledgment). If this register bit is set the acknowledgment frame transmission has to be initiated by the application software using bit SLPTR of register TRXPR. This waiting state is signaled in sub register TRAC_STATUS of register TRX_STATE with value SUCCESS_WAIT_FOR_ACK. RW 0 SLOTTED_OPERATION_BITF CSMA_SEED_0 Transceiver CSMA-CA Random Number Generator Seed Register This register contains the lower 8 bits of the CSMA_SEED. The upper 3 bits are part of register CSMA_SEED_1. CSMA_SEED is the seed for the random number generation that determines the length of the back-off period in the CSMA-CA algorithm. It is recommended to initialize registers CSMA_SEED by random values. This can be done using the bits RND_VALUE of register PHY_RSSI. Note: The register CSMA_SEED_0/1 content initializes the TX_ARET random backoff generator after the wakeup from TRX24 SLEEP state. To prevent a reinitialization with the same value it is recommended to reinitialize both register before every TRX24 SLEEP state with a random value. NA $16D io_flag.bmp Y CSMA_SEED_07 Seed Value for CSMA Random Number Generator These bits contain the bits [7:0] of the CSMA_SEED. RW 1 CSMA_SEED_06 Seed Value for CSMA Random Number Generator These bits contain the bits [7:0] of the CSMA_SEED. RW 1 CSMA_SEED_05 Seed Value for CSMA Random Number Generator These bits contain the bits [7:0] of the CSMA_SEED. RW 1 CSMA_SEED_04 Seed Value for CSMA Random Number Generator These bits contain the bits [7:0] of the CSMA_SEED. RW 0 CSMA_SEED_03 Seed Value for CSMA Random Number Generator These bits contain the bits [7:0] of the CSMA_SEED. RW 1 CSMA_SEED_02 Seed Value for CSMA Random Number Generator These bits contain the bits [7:0] of the CSMA_SEED. RW 0 CSMA_SEED_01 Seed Value for CSMA Random Number Generator These bits contain the bits [7:0] of the CSMA_SEED. RW 1 CSMA_SEED_00 Seed Value for CSMA Random Number Generator These bits contain the bits [7:0] of the CSMA_SEED. RW 0 CSMA_SEED_1 Transceiver Acknowledgment Frame Control Register 2 This register is a control register for RX_AACK and contains a part of the CSMA_SEED for the CSMA-CA algorithm. NA $16E io_flag.bmp Y AACK_FVN_MODE1 Acknowledgment Frame Filter Mode The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of AACK_FVN_MODE specifies the frame filtering behavior of the radio transceiver. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group or independent of the frame version number. Thus the register bits AACK_FVN_MODE define the maximum acceptable frame version. Received frames with a higher frame version number than configured do not pass the address filter and are not acknowledged. RW 0 AACK_FVN_MODE0 Acknowledgment Frame Filter Mode The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of AACK_FVN_MODE specifies the frame filtering behavior of the radio transceiver. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group or independent of the frame version number. Thus the register bits AACK_FVN_MODE define the maximum acceptable frame version. Received frames with a higher frame version number than configured do not pass the address filter and are not acknowledged. RW 1 AACK_FVN_MODE_bitf AACK_SET_PD Set Frame Pending Sub-field The content of AACK_SET_PD bit is copied into the frame pending subfield of the acknowledgment frame if the acknowledgment is the answer to a data request MAC command frame. If in addition the bits AACK_FVN_MODE of this register are configured to accept frames with a frame version other than 0 or 1, the content of register bit AACK_SET_PD is also copied into the frame pending subfield of the acknowledgment frame for any MAC command frame with a frame version of 2 or 3 that have the security enabled subfield set to 1. This is done in the assumption that a future version of the IEEE 802.15.4 standard might change the length or structure of the auxiliary security header, so that it is not possible to safely detect whether the MAC command frame is actually a data request command or not. RW 0 AACK_DIS_ACK Disable Acknowledgment Frame Transmission If this bit is set no acknowledgment frames are transmitted in RX_AACK Extended Operating Mode even if requested. RW 0 AACK_I_AM_COORD Set Personal Area Network Coordinator This register bit has to be set if the node is a PAN coordinator. It is used for address filtering in RX_AACK. RW 0 CSMA_SEED_12 Seed Value for CSMA Random Number Generator These bits contain the bits [10:8] of the CSMA_SEED. The lower part is defined in register CSMA_SEED_0. See register CSMA_SEED_0 for details. RW 0 CSMA_SEED_11 Seed Value for CSMA Random Number Generator These bits contain the bits [10:8] of the CSMA_SEED. The lower part is defined in register CSMA_SEED_0. See register CSMA_SEED_0 for details. RW 1 CSMA_SEED_10 Seed Value for CSMA Random Number Generator These bits contain the bits [10:8] of the CSMA_SEED. The lower part is defined in register CSMA_SEED_0. See register CSMA_SEED_0 for details. RW 0 CSMA_BE Transceiver CSMA-CA Back-off Exponent Control Register This register controls the back-off exponent for the CSMA-CA procedure. NA $16F io_flag.bmp Y MAX_BE3 Maximum Back-off Exponent These register bits define the maximum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are 3 to 8. RW 0 MAX_BE2 Maximum Back-off Exponent These register bits define the maximum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are 3 to 8. RW 1 MAX_BE1 Maximum Back-off Exponent These register bits define the maximum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are 3 to 8. RW 0 MAX_BE0 Maximum Back-off Exponent These register bits define the maximum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are 3 to 8. RW 1 MAX_BE_bitf MIN_BE3 Minimum Back-off Exponent These register bits define the minimum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are MAX_BE, MAX_BE-1), ..., 0. If MIN_BE = 0 and MAX_BE = 0 the CCA back off period is always set to 0. RW 0 MIN_BE2 Minimum Back-off Exponent These register bits define the minimum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are MAX_BE, MAX_BE-1), ..., 0. If MIN_BE = 0 and MAX_BE = 0 the CCA back off period is always set to 0. RW 0 MIN_BE1 Minimum Back-off Exponent These register bits define the minimum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are MAX_BE, MAX_BE-1), ..., 0. If MIN_BE = 0 and MAX_BE = 0 the CCA back off period is always set to 0. RW 1 MIN_BE0 Minimum Back-off Exponent These register bits define the minimum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are MAX_BE, MAX_BE-1), ..., 0. If MIN_BE = 0 and MAX_BE = 0 the CCA back off period is always set to 0. RW 1 MIN_BE_bitf TST_CTRL_DIGI Transceiver Digital Test Control Register This register takes part in the activation sequence of the continuous transmission test mode. Other functionality of this register is reserved for internal use. NA $176 io_flag.bmp Y TST_CTRL_DIG3 Digital Test Controller Register This sub-register selects a test controller function. All values not listed int the following table are reserved for internal use. RW 0 TST_CTRL_DIG2 Digital Test Controller Register This sub-register selects a test controller function. All values not listed int the following table are reserved for internal use. RW 0 TST_CTRL_DIG1 Digital Test Controller Register This sub-register selects a test controller function. All values not listed int the following table are reserved for internal use. RW 0 TST_CTRL_DIG0 Digital Test Controller Register This sub-register selects a test controller function. All values not listed int the following table are reserved for internal use. RW 0 TST_CTRL_DIG_BITF TST_RX_LENGTH Transceiver Received Frame Length Register This register contains the frame length information of a received frame. This information is not stored in the frame buffer. The frame length information is written to this register after the last received octet. NA $17B io_flag.bmp Y RX_LENGTH7 Received Frame Length These bits contain the length of the last received frame. RW 0 RX_LENGTH6 Received Frame Length These bits contain the length of the last received frame. RW 0 RX_LENGTH5 Received Frame Length These bits contain the length of the last received frame. RW 0 RX_LENGTH4 Received Frame Length These bits contain the length of the last received frame. RW 0 RX_LENGTH3 Received Frame Length These bits contain the length of the last received frame. RW 0 RX_LENGTH2 Received Frame Length These bits contain the length of the last received frame. RW 0 RX_LENGTH1 Received Frame Length These bits contain the length of the last received frame. RW 0 RX_LENGTH0 Received Frame Length These bits contain the length of the last received frame. RW 0 TRXFBST Start of frame buffer First byte of the 128 byte long frame buffer of the TRX24. NA $180 io_flag.bmp N TRXFBST7 Frame Buffer Start Byte RW 0 TRXFBST6 Frame Buffer Start Byte RW 0 TRXFBST5 Frame Buffer Start Byte RW 0 TRXFBST4 Frame Buffer Start Byte RW 0 TRXFBST3 Frame Buffer Start Byte RW 0 TRXFBST2 Frame Buffer Start Byte RW 0 TRXFBST1 Frame Buffer Start Byte RW 0 TRXFBST0 Frame Buffer Start Byte RW 0 TRXFBEND End of frame buffer This register is the last byte of the 128 byte long frame buffer of the radio transceiver. NA $1FF io_flag.bmp N TRXFBEND7 Frame Buffer End Byte RW 0 TRXFBEND6 Frame Buffer End Byte RW 0 TRXFBEND5 Frame Buffer End Byte RW 0 TRXFBEND4 Frame Buffer End Byte RW 0 TRXFBEND3 Frame Buffer End Byte RW 0 TRXFBEND2 Frame Buffer End Byte RW 0 TRXFBEND1 Frame Buffer End Byte RW 0 TRXFBEND0 Frame Buffer End Byte RW 0 [SCOCR1HH:SCOCR1HL:SCOCR1LH:SCOCR1LL:SCOCR2HH:SCOCR2HL:SCOCR2LH:SCOCR2LL:SCOCR3HH:SCOCR3HL:SCOCR3LH:SCOCR3LL:SCTSRHH:SCTSRHL:SCTSRLH:SCTSRLL:SCBTSRHH:SCBTSRHL:SCBTSRLH:SCBTSRLL:SCCNTHH:SCCNTHL:SCCNTLH:SCCNTLL:SCCR0:SCCR1:SCSR:SCIRQS:SCIRQM] io_symcnt.bmp SCOCR1HH Symbol Counter Output Compare Register 1 HH-Byte This register contains the most significant byte of the 32 bit compare value for the first compare unit NA $F8 io_flag.bmp Y SCOCR1HH7 Symbol Counter Output Compare Register 1 HH-Byte RW 0 SCOCR1HH6 Symbol Counter Output Compare Register 1 HH-Byte RW 0 SCOCR1HH5 Symbol Counter Output Compare Register 1 HH-Byte RW 0 SCOCR1HH4 Symbol Counter Output Compare Register 1 HH-Byte RW 0 SCOCR1HH3 Symbol Counter Output Compare Register 1 HH-Byte RW 0 SCOCR1HH2 Symbol Counter Output Compare Register 1 HH-Byte RW 0 SCOCR1HH1 Symbol Counter Output Compare Register 1 HH-Byte RW 0 SCOCR1HH0 Symbol Counter Output Compare Register 1 HH-Byte RW 0 SCOCR1HL Symbol Counter Output Compare Register 1 HL-Byte This register contains the second most significant byte of the 32 bit compare value for the first compare unit NA $F7 io_flag.bmp Y SCOCR1HL7 Symbol Counter Output Compare Register 1 HL-Byte RW 0 SCOCR1HL6 Symbol Counter Output Compare Register 1 HL-Byte RW 0 SCOCR1HL5 Symbol Counter Output Compare Register 1 HL-Byte RW 0 SCOCR1HL4 Symbol Counter Output Compare Register 1 HL-Byte RW 0 SCOCR1HL3 Symbol Counter Output Compare Register 1 HL-Byte RW 0 SCOCR1HL2 Symbol Counter Output Compare Register 1 HL-Byte RW 0 SCOCR1HL1 Symbol Counter Output Compare Register 1 HL-Byte RW 0 SCOCR1HL0 Symbol Counter Output Compare Register 1 HL-Byte RW 0 SCOCR1LH Symbol Counter Output Compare Register 1 LH-Byte This register contains the second least significant byte of the 32 bit compare value for the first compare unit NA $F6 io_flag.bmp Y SCOCR1LH7 Symbol Counter Output Compare Register 1 LH-Byte RW 0 SCOCR1LH6 Symbol Counter Output Compare Register 1 LH-Byte RW 0 SCOCR1LH5 Symbol Counter Output Compare Register 1 LH-Byte RW 0 SCOCR1LH4 Symbol Counter Output Compare Register 1 LH-Byte RW 0 SCOCR1LH3 Symbol Counter Output Compare Register 1 LH-Byte RW 0 SCOCR1LH2 Symbol Counter Output Compare Register 1 LH-Byte RW 0 SCOCR1LH1 Symbol Counter Output Compare Register 1 LH-Byte RW 0 SCOCR1LH0 Symbol Counter Output Compare Register 1 LH-Byte RW 0 SCOCR1LL Symbol Counter Output Compare Register 1 LL-Byte This register contains the least significant byte of the 32 bit compare value for the first compare unit NA $F5 io_flag.bmp Y SCOCR1LL7 Symbol Counter Output Compare Register 1 LL-Byte RW 0 SCOCR1LL6 Symbol Counter Output Compare Register 1 LL-Byte RW 0 SCOCR1LL5 Symbol Counter Output Compare Register 1 LL-Byte RW 0 SCOCR1LL4 Symbol Counter Output Compare Register 1 LL-Byte RW 0 SCOCR1LL3 Symbol Counter Output Compare Register 1 LL-Byte RW 0 SCOCR1LL2 Symbol Counter Output Compare Register 1 LL-Byte RW 0 SCOCR1LL1 Symbol Counter Output Compare Register 1 LL-Byte RW 0 SCOCR1LL0 Symbol Counter Output Compare Register 1 LL-Byte RW 0 SCOCR2HH Symbol Counter Output Compare Register 2 HH-Byte This register contains the most significant byte of the 32 bit compare value for the second compare unit NA $F4 io_flag.bmp Y SCOCR2HH7 Symbol Counter Output Compare Register 2 HH-Byte RW 0 SCOCR2HH6 Symbol Counter Output Compare Register 2 HH-Byte RW 0 SCOCR2HH5 Symbol Counter Output Compare Register 2 HH-Byte RW 0 SCOCR2HH4 Symbol Counter Output Compare Register 2 HH-Byte RW 0 SCOCR2HH3 Symbol Counter Output Compare Register 2 HH-Byte RW 0 SCOCR2HH2 Symbol Counter Output Compare Register 2 HH-Byte RW 0 SCOCR2HH1 Symbol Counter Output Compare Register 2 HH-Byte RW 0 SCOCR2HH0 Symbol Counter Output Compare Register 2 HH-Byte RW 0 SCOCR2HL Symbol Counter Output Compare Register 2 HL-Byte This register contains the second most significant byte of the 32 bit compare value for the second compare unit NA $F3 io_flag.bmp Y SCOCR2HL7 Symbol Counter Output Compare Register 2 HL-Byte RW 0 SCOCR2HL6 Symbol Counter Output Compare Register 2 HL-Byte RW 0 SCOCR2HL5 Symbol Counter Output Compare Register 2 HL-Byte RW 0 SCOCR2HL4 Symbol Counter Output Compare Register 2 HL-Byte RW 0 SCOCR2HL3 Symbol Counter Output Compare Register 2 HL-Byte RW 0 SCOCR2HL2 Symbol Counter Output Compare Register 2 HL-Byte RW 0 SCOCR2HL1 Symbol Counter Output Compare Register 2 HL-Byte RW 0 SCOCR2HL0 Symbol Counter Output Compare Register 2 HL-Byte RW 0 SCOCR2LH Symbol Counter Output Compare Register 2 LH-Byte This register contains the second least significant byte of the 32 bit compare value for the second compare unit NA $F2 io_flag.bmp Y SCOCR2LH7 Symbol Counter Output Compare Register 2 LH-Byte RW 0 SCOCR2LH6 Symbol Counter Output Compare Register 2 LH-Byte RW 0 SCOCR2LH5 Symbol Counter Output Compare Register 2 LH-Byte RW 0 SCOCR2LH4 Symbol Counter Output Compare Register 2 LH-Byte RW 0 SCOCR2LH3 Symbol Counter Output Compare Register 2 LH-Byte RW 0 SCOCR2LH2 Symbol Counter Output Compare Register 2 LH-Byte RW 0 SCOCR2LH1 Symbol Counter Output Compare Register 2 LH-Byte RW 0 SCOCR2LH0 Symbol Counter Output Compare Register 2 LH-Byte RW 0 SCOCR2LL Symbol Counter Output Compare Register 2 LL-Byte This register contains the least significant byte of the 32 bit compare value for the second compare unit NA $F1 io_flag.bmp Y SCOCR2LL7 Symbol Counter Output Compare Register 2 LL-Byte RW 0 SCOCR2LL6 Symbol Counter Output Compare Register 2 LL-Byte RW 0 SCOCR2LL5 Symbol Counter Output Compare Register 2 LL-Byte RW 0 SCOCR2LL4 Symbol Counter Output Compare Register 2 LL-Byte RW 0 SCOCR2LL3 Symbol Counter Output Compare Register 2 LL-Byte RW 0 SCOCR2LL2 Symbol Counter Output Compare Register 2 LL-Byte RW 0 SCOCR2LL1 Symbol Counter Output Compare Register 2 LL-Byte RW 0 SCOCR2LL0 Symbol Counter Output Compare Register 2 LL-Byte RW 0 SCOCR3HH Symbol Counter Output Compare Register 3 HH-Byte This register contains the most significant byte of the 32 bit compare value for the third compare unit NA $F0 io_flag.bmp Y SCOCR3HH7 Symbol Counter Output Compare Register 3 HH-Byte RW 0 SCOCR3HH6 Symbol Counter Output Compare Register 3 HH-Byte RW 0 SCOCR3HH5 Symbol Counter Output Compare Register 3 HH-Byte RW 0 SCOCR3HH4 Symbol Counter Output Compare Register 3 HH-Byte RW 0 SCOCR3HH3 Symbol Counter Output Compare Register 3 HH-Byte RW 0 SCOCR3HH2 Symbol Counter Output Compare Register 3 HH-Byte RW 0 SCOCR3HH1 Symbol Counter Output Compare Register 3 HH-Byte RW 0 SCOCR3HH0 Symbol Counter Output Compare Register 3 HH-Byte RW 0 SCOCR3HL Symbol Counter Output Compare Register 3 HL-Byte This register contains the second most significant byte of the 32 bit compare value for the third compare unit NA $EF io_flag.bmp Y SCOCR3HL7 Symbol Counter Output Compare Register 3 HL-Byte RW 0 SCOCR3HL6 Symbol Counter Output Compare Register 3 HL-Byte RW 0 SCOCR3HL5 Symbol Counter Output Compare Register 3 HL-Byte RW 0 SCOCR3HL4 Symbol Counter Output Compare Register 3 HL-Byte RW 0 SCOCR3HL3 Symbol Counter Output Compare Register 3 HL-Byte RW 0 SCOCR3HL2 Symbol Counter Output Compare Register 3 HL-Byte RW 0 SCOCR3HL1 Symbol Counter Output Compare Register 3 HL-Byte RW 0 SCOCR3HL0 Symbol Counter Output Compare Register 3 HL-Byte RW 0 SCOCR3LH Symbol Counter Output Compare Register 3 LH-Byte This register contains the second least significant byte of the 32 bit compare value for the third compare unit NA $EE io_flag.bmp Y SCOCR3LH7 Symbol Counter Output Compare Register 3 LH-Byte RW 0 SCOCR3LH6 Symbol Counter Output Compare Register 3 LH-Byte RW 0 SCOCR3LH5 Symbol Counter Output Compare Register 3 LH-Byte RW 0 SCOCR3LH4 Symbol Counter Output Compare Register 3 LH-Byte RW 0 SCOCR3LH3 Symbol Counter Output Compare Register 3 LH-Byte RW 0 SCOCR3LH2 Symbol Counter Output Compare Register 3 LH-Byte RW 0 SCOCR3LH1 Symbol Counter Output Compare Register 3 LH-Byte RW 0 SCOCR3LH0 Symbol Counter Output Compare Register 3 LH-Byte RW 0 SCOCR3LL Symbol Counter Output Compare Register 3 LL-Byte This register contains the least significant byte of the 32 bit compare value for the third compare unit NA $ED io_flag.bmp Y SCOCR3LL7 Symbol Counter Output Compare Register 3 LL-Byte RW 0 SCOCR3LL6 Symbol Counter Output Compare Register 3 LL-Byte RW 0 SCOCR3LL5 Symbol Counter Output Compare Register 3 LL-Byte RW 0 SCOCR3LL4 Symbol Counter Output Compare Register 3 LL-Byte RW 0 SCOCR3LL3 Symbol Counter Output Compare Register 3 LL-Byte RW 0 SCOCR3LL2 Symbol Counter Output Compare Register 3 LL-Byte RW 0 SCOCR3LL1 Symbol Counter Output Compare Register 3 LL-Byte RW 0 SCOCR3LL0 Symbol Counter Output Compare Register 3 LL-Byte RW 0 SCTSRHH Symbol Counter Frame Timestamp Register HH-Byte This register contains the most significant byte of the 32 bit frame (SFD) timestamp register NA $EC io_flag.bmp Y SCTSRHH7 Symbol Counter Frame Timestamp Register HH-Byte R 0 SCTSRHH6 Symbol Counter Frame Timestamp Register HH-Byte R 0 SCTSRHH5 Symbol Counter Frame Timestamp Register HH-Byte R 0 SCTSRHH4 Symbol Counter Frame Timestamp Register HH-Byte R 0 SCTSRHH3 Symbol Counter Frame Timestamp Register HH-Byte R 0 SCTSRHH2 Symbol Counter Frame Timestamp Register HH-Byte R 0 SCTSRHH1 Symbol Counter Frame Timestamp Register HH-Byte R 0 SCTSRHH0 Symbol Counter Frame Timestamp Register HH-Byte R 0 SCTSRHL Symbol Counter Frame Timestamp Register HL-Byte This register contains the second most significant byte of the 32 bit Frame (SFD) Timestamp Register NA $EB io_flag.bmp Y SCTSRHL7 Symbol Counter Frame Timestamp Register HL-Byte R 0 SCTSRHL6 Symbol Counter Frame Timestamp Register HL-Byte R 0 SCTSRHL5 Symbol Counter Frame Timestamp Register HL-Byte R 0 SCTSRHL4 Symbol Counter Frame Timestamp Register HL-Byte R 0 SCTSRHL3 Symbol Counter Frame Timestamp Register HL-Byte R 0 SCTSRHL2 Symbol Counter Frame Timestamp Register HL-Byte R 0 SCTSRHL1 Symbol Counter Frame Timestamp Register HL-Byte R 0 SCTSRHL0 Symbol Counter Frame Timestamp Register HL-Byte R 0 SCTSRLH Symbol Counter Frame Timestamp Register LH-Byte This register contains the second least significant byte of the 32 bit Frame (SFD) Timestamp Register NA $EA io_flag.bmp Y SCTSRLH7 Symbol Counter Frame Timestamp Register LH-Byte R 0 SCTSRLH6 Symbol Counter Frame Timestamp Register LH-Byte R 0 SCTSRLH5 Symbol Counter Frame Timestamp Register LH-Byte R 0 SCTSRLH4 Symbol Counter Frame Timestamp Register LH-Byte R 0 SCTSRLH3 Symbol Counter Frame Timestamp Register LH-Byte R 0 SCTSRLH2 Symbol Counter Frame Timestamp Register LH-Byte R 0 SCTSRLH1 Symbol Counter Frame Timestamp Register LH-Byte R 0 SCTSRLH0 Symbol Counter Frame Timestamp Register LH-Byte R 0 SCTSRLL Symbol Counter Frame Timestamp Register LL-Byte This register contains the least significant byte of the 32 bit Frame (SFD) Timestamp Register NA $E9 io_flag.bmp Y SCTSRLL7 Symbol Counter Frame Timestamp Register LL-Byte R 0 SCTSRLL6 Symbol Counter Frame Timestamp Register LL-Byte R 0 SCTSRLL5 Symbol Counter Frame Timestamp Register LL-Byte R 0 SCTSRLL4 Symbol Counter Frame Timestamp Register LL-Byte R 0 SCTSRLL3 Symbol Counter Frame Timestamp Register LL-Byte R 0 SCTSRLL2 Symbol Counter Frame Timestamp Register LL-Byte R 0 SCTSRLL1 Symbol Counter Frame Timestamp Register LL-Byte R 0 SCTSRLL0 Symbol Counter Frame Timestamp Register LL-Byte R 0 SCBTSRHH Symbol Counter Beacon Timestamp Register HH-Byte This register contains the most significant byte of the 32 bit Beacon Timestamp Register. The Beacon Timestamp Register is updated with the contents of the Frame Timestamp Register if the received frame was a valid beacon frame with matching source PAN identifier or register {PAN_ID_1, PAN_ID_0} = 0xFFFF. NA $E8 io_flag.bmp Y SCBTSRHH7 Symbol Counter Beacon Timestamp Register HH-Byte RW 0 SCBTSRHH6 Symbol Counter Beacon Timestamp Register HH-Byte RW 0 SCBTSRHH5 Symbol Counter Beacon Timestamp Register HH-Byte RW 0 SCBTSRHH4 Symbol Counter Beacon Timestamp Register HH-Byte RW 0 SCBTSRHH3 Symbol Counter Beacon Timestamp Register HH-Byte RW 0 SCBTSRHH2 Symbol Counter Beacon Timestamp Register HH-Byte RW 0 SCBTSRHH1 Symbol Counter Beacon Timestamp Register HH-Byte RW 0 SCBTSRHH0 Symbol Counter Beacon Timestamp Register HH-Byte RW 0 SCBTSRHL Symbol Counter Beacon Timestamp Register HL-Byte This register contains the second most significant byte of the 32 bit Beacon Timestamp Register. NA $E7 io_flag.bmp Y SCBTSRHL7 Symbol Counter Beacon Timestamp Register HL-Byte RW 0 SCBTSRHL6 Symbol Counter Beacon Timestamp Register HL-Byte RW 0 SCBTSRHL5 Symbol Counter Beacon Timestamp Register HL-Byte RW 0 SCBTSRHL4 Symbol Counter Beacon Timestamp Register HL-Byte RW 0 SCBTSRHL3 Symbol Counter Beacon Timestamp Register HL-Byte RW 0 SCBTSRHL2 Symbol Counter Beacon Timestamp Register HL-Byte RW 0 SCBTSRHL1 Symbol Counter Beacon Timestamp Register HL-Byte RW 0 SCBTSRHL0 Symbol Counter Beacon Timestamp Register HL-Byte RW 0 SCBTSRLH Symbol Counter Beacon Timestamp Register LH-Byte This register contains the second least significant byte of the 32 bit Beacon Timestamp Register. NA $E6 io_flag.bmp Y SCBTSRLH7 Symbol Counter Beacon Timestamp Register LH-Byte RW 0 SCBTSRLH6 Symbol Counter Beacon Timestamp Register LH-Byte RW 0 SCBTSRLH5 Symbol Counter Beacon Timestamp Register LH-Byte RW 0 SCBTSRLH4 Symbol Counter Beacon Timestamp Register LH-Byte RW 0 SCBTSRLH3 Symbol Counter Beacon Timestamp Register LH-Byte RW 0 SCBTSRLH2 Symbol Counter Beacon Timestamp Register LH-Byte RW 0 SCBTSRLH1 Symbol Counter Beacon Timestamp Register LH-Byte RW 0 SCBTSRLH0 Symbol Counter Beacon Timestamp Register LH-Byte RW 0 SCBTSRLL Symbol Counter Beacon Timestamp Register LL-Byte This register contains the least significant byte of the 32 bit Beacon Timestamp Register. NA $E5 io_flag.bmp Y SCBTSRLL7 Symbol Counter Beacon Timestamp Register LL-Byte RW 0 SCBTSRLL6 Symbol Counter Beacon Timestamp Register LL-Byte RW 0 SCBTSRLL5 Symbol Counter Beacon Timestamp Register LL-Byte RW 0 SCBTSRLL4 Symbol Counter Beacon Timestamp Register LL-Byte RW 0 SCBTSRLL3 Symbol Counter Beacon Timestamp Register LL-Byte RW 0 SCBTSRLL2 Symbol Counter Beacon Timestamp Register LL-Byte RW 0 SCBTSRLL1 Symbol Counter Beacon Timestamp Register LL-Byte RW 0 SCBTSRLL0 Symbol Counter Beacon Timestamp Register LL-Byte RW 0 SCCNTHH Symbol Counter Register HH-Byte This register contains the most significant byte of the 32 bit Symbol Counter. NA $E4 io_flag.bmp Y SCCNTHH7 Symbol Counter Register HH-Byte RW 0 SCCNTHH6 Symbol Counter Register HH-Byte RW 0 SCCNTHH5 Symbol Counter Register HH-Byte RW 0 SCCNTHH4 Symbol Counter Register HH-Byte RW 0 SCCNTHH3 Symbol Counter Register HH-Byte RW 0 SCCNTHH2 Symbol Counter Register HH-Byte RW 0 SCCNTHH1 Symbol Counter Register HH-Byte RW 0 SCCNTHH0 Symbol Counter Register HH-Byte RW 0 SCCNTHL Symbol Counter Register HL-Byte This register contains the second most significant byte of the 32 bit Symbol Counter. NA $E3 io_flag.bmp Y SCCNTHL7 Symbol Counter Register HL-Byte RW 0 SCCNTHL6 Symbol Counter Register HL-Byte RW 0 SCCNTHL5 Symbol Counter Register HL-Byte RW 0 SCCNTHL4 Symbol Counter Register HL-Byte RW 0 SCCNTHL3 Symbol Counter Register HL-Byte RW 0 SCCNTHL2 Symbol Counter Register HL-Byte RW 0 SCCNTHL1 Symbol Counter Register HL-Byte RW 0 SCCNTHL0 Symbol Counter Register HL-Byte RW 0 SCCNTLH Symbol Counter Register LH-Byte This register contains the second least significant byte of the 32 bit Symbol Counter. NA $E2 io_flag.bmp Y SCCNTLH7 Symbol Counter Register LH-Byte RW 0 SCCNTLH6 Symbol Counter Register LH-Byte RW 0 SCCNTLH5 Symbol Counter Register LH-Byte RW 0 SCCNTLH4 Symbol Counter Register LH-Byte RW 0 SCCNTLH3 Symbol Counter Register LH-Byte RW 0 SCCNTLH2 Symbol Counter Register LH-Byte RW 0 SCCNTLH1 Symbol Counter Register LH-Byte RW 0 SCCNTLH0 Symbol Counter Register LH-Byte RW 0 SCCNTLL Symbol Counter Register LL-Byte This register contains the least significant byte of the 32 bit Symbol Counter. NA $E1 io_flag.bmp Y SCCNTLL7 Symbol Counter Register LL-Byte RW 0 SCCNTLL6 Symbol Counter Register LL-Byte RW 0 SCCNTLL5 Symbol Counter Register LL-Byte RW 0 SCCNTLL4 Symbol Counter Register LL-Byte RW 0 SCCNTLL3 Symbol Counter Register LL-Byte RW 0 SCCNTLL2 Symbol Counter Register LL-Byte RW 0 SCCNTLL1 Symbol Counter Register LL-Byte RW 0 SCCNTLL0 Symbol Counter Register LL-Byte RW 0 SCIRQS Symbol Counter Interrupt Status Register The Interrupt Status Register indicates pending interrupt requests. If the corresponding interrupt mask bit is set, an interrupt service routine is called and the status bit is cleared automatically. It is also possible to clear the status bit by writing "1" to the selected bit. NA $E0 io_flag.bmp Y Res2 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res1 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res0 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 IRQSBO Backoff Slot Counter IRQ This interrupt is generated every 320 µs, that means every 20 symbols. RW 0 IRQSOF Symbol Counter Overflow IRQ This interrupt is generated when the 32 bit counter turns from 0xFFFFFFF to 0x00000000. RW 0 IRQSCP3 Compare Unit 3 Compare Match IRQ This interrupt indicates a compare match on compare unit 3. RW 0 IRQSCP2 Compare Unit 2 Compare Match IRQ This interrupt indicates a compare match on compare unit 2. RW 0 IRQSCP1 Compare Unit 1 Compare Match IRQ This interrupt indicates a compare match on compare unit 1. RW 0 SCIRQM Symbol Counter Interrupt Mask Register The Interrupt Mask Register is used to enable corresponding interrupts. After reset all interrupts are disabled. Disabled interrupts are still captured in the interrupt status register SCIRQS, but no interrupt is requested. Before enabling an interrupt, the corresponding interrupt status bit should be cleared by writing a 1. If the status bit is set and the IRQ gets enabled, the IRQ handler is called immediatly. NA $DF io_flag.bmp Y Res2 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res1 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res0 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 IRQMBO Backoff Slot Counter IRQ enable This bit enables the SCNT_BACKOFF interrupt. RW 0 IRQMOF Symbol Counter Overflow IRQ enable This bit enables the SCNT_OVFL interrupt. RW 0 IRQMCP3 Symbol Counter Compare Match 3 IRQ enable This bit enables the SCNT_CMP3 interrupt. RW 0 IRQMCP2 Symbol Counter Compare Match 2 IRQ enable This bit enables the SCNT_CMP2 interrupt. RW 0 IRQMCP1 Symbol Counter Compare Match 1 IRQ enable This bit enables the SCNT_CMP1 interrupt. RW 0 SCSR Symbol Counter Status Register NA $DE io_flag.bmp Y Res6 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res5 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res4 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res3 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res2 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res1 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res0 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 SCBSY Symbol Counter busy This bit is set if a write operation to the symbol counter register is pending. This bit is set after writing the counter low byte (SCCNTLL) until the symbol counter is updated with the new value. This update process can take up to 16 µs and during this time no read or write access to the 32 bit counter register should occure. R 0 SCCR1 Symbol Counter Control Register 1 This register is used to enable the backoff slot counter. NA $DD io_flag.bmp Y Res6 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res5 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res4 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res3 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res2 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res1 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 Res0 Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. R 0 SCENBO Backoff Slot Counter enable If this bit is set, the backoff slot counter starts working. To enable the corresponding IRQ the SCIRQM register must be updated. RW 0 SCCR0 Symbol Counter Control Register 0 The Control Register 0 is used to setup the operating mode of the symbol counter and the compare units NA $DC io_flag.bmp Y SCRES Symbol Counter Synchronization If this bit is set to 1, the 16 MHz clock prescaler as well as the backoff slot counter is cleared. This function can be used to align the symbol timing within one 16 µs symbol period and to restart the backoff slot counter with a complete 320 µs period. This feature works only if the symbol counter module operates with the 16 MHz clock from XTAL1. After switching to RTC clock source, the symbol period synchronization is lost. This bit is cleared automatically. RW 0 SCMBTS Manual Beacon Timestamp With this bit a manual beacon timestamp can be generated. If set to 1, the current symbol counter value is stored into the beacon timestamp register. The bit is cleared afterwards. The manual beacon timestamping can be used in conjunction with the relative compare mode of the three compare units to generate compare match interrupts without having a beacon frame received. RW 0 SCEN Symbol Counter enable This bit activates the symbol counter module. If the bit is not set, the counter, backoff slot counter and the compare unit are disabled and disconnected from the clock. In this way the power consumption can be reduced. All registers can be accessed, but write access to the counter register SCCNT is not possible. RW 0 SCCKSEL Symbol Counter Clock Source select With this bit the clock source for the symbol counter can be selected. If the bit is one, the RTC clock from TOSC1 is selected, otherwise the symbol counter operates with the clock from XTAL1. During transceiver sleep modes the clock falls back to the RTC clock source, regardless of the selected clock. After wakeup, it switches back to the previosly selected clock source. RW 0 SCTSE Symbol Counter Automatic Timestamping enable This bit enables automatic SFD and Beacon Timestamping. If the bit is zero, no automatic timestamp capturing is possible. Only manual beacon timestamping can be used. RW 0 SCCMP3 Symbol Counter Compare Unit 3 Mode select This bit enables the relative compare mode for compare unit 3. If enabled, the counter value is compared against the content of the beacon timestamp register plus the content of the compare register 3 (SCCNT == SCBTS+SCOCR3). Otherwise, the counter is compared against the copare register 3 (SCCNT == SCOCR3). RW 0 SCCMP2 Symbol Counter Compare Unit 2 Mode select This bit enables the relative compare mode for compare unit 2. If enabled, the counter value is compared against the content of the beacon timestamp register plus the content of the compare register 2 (SCCNT == SCBTS+SCOCR2). Otherwise, the counter is compared against the copare register 2 (SCCNT == SCOCR2). RW 0 SCCMP1 Symbol Counter Compare Unit 1 Mode select This bit enables the relative compare mode for compare unit 1. If enabled, the counter value is compared against the content of the beacon timestamp register plus the content of the compare register 1 (SCCNT == SCBTS+SCOCR1). Otherwise, the counter is compared against the copare register 1 (SCCNT == SCOCR1). RW 0 [EEARH:EEARL:EEDR:EECR] io_cpu.bmp The EEPROM is the nonvolatile data memory of the device. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM Access Registers are accessible in the I/O space. A self-timing function lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. The calibrated Oscillator is used to time the EEPROM accesses. EEARH EEPROM Address Register High Byte The EEPROM Address Registers EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $22 $42 io_cpu.bmp N Res3 Reserved R 0 Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 EEAR11 EEPROM Address RW X EEAR10 EEPROM Address RW X EEAR9 EEPROM Address RW X EEAR8 EEPROM Address RW X EEPROM_ADDRESS_BITF EEARL EEPROM Address Register Low Byte The EEPROM Address Registers EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $21 $41 io_cpu.bmp N EEAR7 EEPROM Address RW X EEAR6 EEPROM Address RW X EEAR5 EEPROM Address RW X EEAR4 EEPROM Address RW X EEAR3 EEPROM Address RW X EEAR2 EEPROM Address RW X EEAR1 EEPROM Address RW X EEAR0 EEPROM Address RW X EEPROM_ADDRESS_BITF EEDR EEPROM Data Register For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $20 $40 io_cpu.bmp N EEDR7 EEPROM Data RW 0 EEDR6 EEPROM Data RW 0 EEDR5 EEPROM Data RW 0 EEDR4 EEPROM Data RW 0 EEDR3 EEPROM Data RW 0 EEDR2 EEPROM Data RW 0 EEDR1 EEPROM Data RW 0 EEDR0 EEPROM Data RW 0 EEPROM_DATA_BITF EECR EEPROM Control Register $1F $3F io_flag.bmp Y Res1 Reserved R 0 Res0 Reserved R 0 EEPM1 EEPROM Programming Mode The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in the following table. While EEPE is set, any write to EEPM1:0 will be ignored. During reset, the EEPM1:0 bits will be reset to 0 unless the EEPROM is busy programming. RW X EEPM0 EEPROM Programming Mode The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in the following table. While EEPE is set, any write to EEPM1:0 will be ignored. During reset, the EEPM1:0 bits will be reset to 0 unless the EEPROM is busy programming. RW EEP_MODE2 X EERIE EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared. RW 0 EEMPE EEPROM Master Write Enable The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure. RW 0 EEPE EEPROM Programming Enable The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be adopted when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEPE becomes zero. 2. Wait until SPMEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR. 6. Within four clock cycles after setting EEMPE, write a logical one to EEPE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. Caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all steps to avoid these problems. When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. RW X EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM nor to change the EEAR Register. RW 0 [OCDR:MCUCR:MCUSR] io_com.bmp 00 The AVR IEEE std. 1149.1 compliant JTAG interface can be used for Testing PCBs by using the JTAG Boundary-scan capability, Programming the non-volatile memories, Fuses and Lock bits and On-chip debugging. Its main features are: Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard; Debugger Access to all Internal Peripheral Units, the internal and external RAM, the Internal Register File, the Program Counter and the EEPROM and Flash Memories; Extensive On-chip Debug Support for Break Conditions, Including AVR Break Instruction, Break on Change of Program Memory Flow, Single Step Break, Program Memory Break Points on Single Address or Address Range and Data Memory Break Points on Single Address or Address Range; Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface; On-chip Debugging Supported by AVR Studio. OCDR On-Chip Debug Register The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal flag; I/O Debug Register Dirty IDRD is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information. In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables access to the OCDR Register. In all other cases, the standard I/O location is accessed. $31 $51 io_com.bmp Y OCDR7 IDRD On-Chip Debug Register Data RW 0 OCDR6 On-Chip Debug Register Data RW 0 OCDR5 On-Chip Debug Register Data RW 0 OCDR4 On-Chip Debug Register Data RW 0 OCDR3 On-Chip Debug Register Data RW 0 OCDR2 On-Chip Debug Register Data RW 0 OCDR1 On-Chip Debug Register Data RW 0 OCDR0 On-Chip Debug Register Data RW 0 OCDR_DATA_BITF MCUCR MCU Control Register The MCU Control Register contains control bits for general Microcontroller Unit functions. $35 $55 io_flag.bmp Y JTD JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value. Note that this bit must not be altered when using the On-chip Debug system. RW 0 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. $34 $54 io_flag.bmp Y JTRF JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. RW 0 [EICRA:EICRB:EIMSK:EIFR:PCICR:PCIFR:PCMSK2:PCMSK1:PCMSK0] [PCMSK2:PCMSK1:PCMSK0] io_ext.bmp The External Interrupts are triggered by the INT7:0 pin or any of the PCINT8:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT8:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The Pin change interrupt PCI1 will trigger if the enabled PCINT8 pin toggles PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT8:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the "External Interrupt Control Registers EICRA" (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in section "System Clock and Clock Options". EICRA External Interrupt Control Register A The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in the following tables. Edges on INT3:0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width of typical 50 ns will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. NA $69 io_flag.bmp Y ISC31 External Interrupt 3 Sense Control Bit RW 0 ISC30 External Interrupt 3 Sense Control Bit RW INTERRUPT_SENSE_CONTROL3 0 ISC21 External Interrupt 2 Sense Control Bit RW 0 ISC20 External Interrupt 2 Sense Control Bit RW INTERRUPT_SENSE_CONTROL3 0 ISC11 External Interrupt 1 Sense Control Bit RW 0 ISC10 External Interrupt 1 Sense Control Bit RW INTERRUPT_SENSE_CONTROL3 0 ISC01 External Interrupt 0 Sense Control Bit RW 0 ISC00 External Interrupt 0 Sense Control Bit RW INTERRUPT_SENSE_CONTROL3 0 EICRB External Interrupt Control Register B The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in the following tables. Edges on INT7:4 are registered asynchronously. Pulses on INT7:4 pins wider than the minimum pulse width of typical 50 ns will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. NA $6A io_flag.bmp Y ISC71 External Interrupt 7 Sense Control Bit RW 0 ISC70 External Interrupt 7 Sense Control Bit RW INTERRUPT_SENSE_CONTROL3 0 ISC61 External Interrupt 6 Sense Control Bit RW 0 ISC60 External Interrupt 6 Sense Control Bit RW INTERRUPT_SENSE_CONTROL3 0 ISC51 External Interrupt 5 Sense Control Bit RW 0 ISC50 External Interrupt 5 Sense Control Bit RW INTERRUPT_SENSE_CONTROL3 0 ISC41 External Interrupt 4 Sense Control Bit RW 0 ISC40 External Interrupt 4 Sense Control Bit RW INTERRUPT_SENSE_CONTROL3 0 EIMSK External Interrupt Mask Register When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers EICRA and EICRB define whether the External Interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. $1D $3D io_flag.bmp Y INT7 External Interrupt Request Enable RW 0 INT6 External Interrupt Request Enable RW 0 INT5 External Interrupt Request Enable RW 0 INT4 External Interrupt Request Enable RW 0 INT3 External Interrupt Request Enable RW 0 INT2 External Interrupt Request Enable RW 0 INT1 External Interrupt Request Enable RW 0 INT0 External Interrupt Request Enable RW 0 INTERRUPT_REQ_ENABLE_BITF EIFR External Interrupt Flag Register When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit INT7:0 in EIMSK are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See "Digital Input Enable and Sleep Modes" for more information. $1C $3C io_flag.bmp Y INTF7 External Interrupt Flag RW 0 INTF6 External Interrupt Flag RW 0 INTF5 External Interrupt Flag RW 0 INTF4 External Interrupt Flag RW 0 INTF3 External Interrupt Flag RW 0 INTF2 External Interrupt Flag RW 0 INTF1 External Interrupt Flag RW 0 INTF0 External Interrupt Flag RW 0 INTERRUPT_EXT_FLAG_BITF PCMSK2 Pin Change Mask Register 2 Note that the PCMSK2 register has no function in this device. The I/O ports associated to PCINT23:16 are not implemented. Normally each bit PCINT23:16 selects whether the pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, the pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is cleared, the pin change interrupt on the corresponding I/O pin is disabled. NA $6D io_flag.bmp Y PCINT23 Pin Change Enable Mask RW 0 PCINT22 Pin Change Enable Mask RW 0 PCINT21 Pin Change Enable Mask RW 0 PCINT20 Pin Change Enable Mask RW 0 PCINT19 Pin Change Enable Mask RW 0 PCINT18 Pin Change Enable Mask RW 0 PCINT17 Pin Change Enable Mask RW 0 PCINT16 Pin Change Enable Mask RW 0 PCMSK1 Pin Change Mask Register 1 Bit PCINT8 selects whether the pin change interrupt is enabled on the corresponding I/O pin. If PCINT8 is set and the PCIE1 bit in PCICR is set, the pin change interrupt is enabled on the corresponding I/O pin. If PCINT8 is cleared, the pin change interrupt on the corresponding I/O pin is disabled. NA $6C io_flag.bmp Y PCINT15 Pin Change Enable Mask Bits 15:9 of the PCMSK1 register have no function in this device. The I/O ports associated to PCINT15:9 are not implemented. RW 0 PCINT14 Pin Change Enable Mask Bits 15:9 of the PCMSK1 register have no function in this device. The I/O ports associated to PCINT15:9 are not implemented. RW 0 PCINT13 Pin Change Enable Mask Bits 15:9 of the PCMSK1 register have no function in this device. The I/O ports associated to PCINT15:9 are not implemented. RW 0 PCINT12 Pin Change Enable Mask Bits 15:9 of the PCMSK1 register have no function in this device. The I/O ports associated to PCINT15:9 are not implemented. RW 0 PCINT11 Pin Change Enable Mask Bits 15:9 of the PCMSK1 register have no function in this device. The I/O ports associated to PCINT15:9 are not implemented. RW 0 PCINT10 Pin Change Enable Mask Bits 15:9 of the PCMSK1 register have no function in this device. The I/O ports associated to PCINT15:9 are not implemented. RW 0 PCINT9 Pin Change Enable Mask Bits 15:9 of the PCMSK1 register have no function in this device. The I/O ports associated to PCINT15:9 are not implemented. RW 0 PCINT8 Pin Change Enable Mask 8 If this bit is set to one the pin change interrupt on the corresponding I/O pin is enabled. If this bit is set to zero the pin change interrupt is disabled. RW 0 PCMSK0 Pin Change Mask Register 0 Each bit PCINT7:0 selects whether the pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, the pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is cleared, the pin change interrupt on the corresponding I/O pin is disabled. NA $6B io_flag.bmp N PCINT7 Pin Change Enable Mask RW 0 PCINT6 Pin Change Enable Mask RW 0 PCINT5 Pin Change Enable Mask RW 0 PCINT4 Pin Change Enable Mask RW 0 PCINT3 Pin Change Enable Mask RW 0 PCINT2 Pin Change Enable Mask RW 0 PCINT1 Pin Change Enable Mask RW 0 PCINT0 Pin Change Enable Mask RW 0 INTERRUPT_PCMSK_BITF PCIFR Pin Change Interrupt Flag Register $1B $3B io_flag.bmp Y Res4 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res3 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 PCIF2 Pin Change Interrupt Flag 2 When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. Note that the I/O ports corresponding to PCINT23:16 are not implemented. Therefore PCIF2 has no function in this device. RW 0 PCIF1 Pin Change Interrupt Flag 1 When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. Note that the I/O ports corresponding to PCINT15:9 are not implemented. RW 0 PCIF0 Pin Change Interrupt Flag 0 When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCICR Pin Change Interrupt Control Register NA $68 io_flag.bmp Y Res4 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res3 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 PCIE2 Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register. Note that the I/O ports corresponding to PCINT23:16 are not implemented. Therefore PCIE2 has no function in this device. RW 0 PCIE1 Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15:8 pins are enabled individually by the PCMSK1 Register. Note that the I/O ports corresponding to PCINT15:9 are not implemented. RW 0 PCIE0 Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register. RW 0 [ADMUX:ADCSRA:ADCSRB:ADCSRC:ADCH:ADCL:DIDR0:DIDR2] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD converter feature list: 10-bit resolution. 2 LSB integral non-linearity. +/-4 LSB absolute accuracy. 3 - 240 us conversion time. Up to 330 kSPS at maximum resolution. 8 multiplexed single-ended input channels. 7 differential input channels. 2 differential input channels with an optional gain of 10x and 200x. Internal linear temperature sensor. Optional left adjustment for ADC result readout. 0 - AVDD ADC input voltage range. 0 - EVDD differential ADC input voltage range. Selectable 1.5 V, 1.6 V or AVDD ADC reference voltage. Free running or single conversion mode. Interrupt on AD conversion complete. Sleep mode noise canceller. ADMUX The ADC Multiplexer Selection Register NA $7C io_analo.bmp Y REFS1 Reference Selection Bits These bits select the voltage reference for the ADC. Changes of these bits will only take effect until the first conversion start is requested by setting ADSC. After this the ADC has to be disabled and enabled again for new reference selections. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 REFS0 Reference Selection Bits These bits select the voltage reference for the ADC. Changes of these bits will only take effect until the first conversion start is requested by setting ADSC. After this the ADC has to be disabled and enabled again for new reference selections. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW ANALOG_ADC_V_REF9 0 ADLAR ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ADCL and ADCH register description. RW 0 MUX4 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs is connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Note that the MUX5 bit is located in the ADCSRB register. A write access to the MUX4:0 bits triggers the update of the internally buffered MUX5 bit. RW 0 MUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs is connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Note that the MUX5 bit is located in the ADCSRB register. A write access to the MUX4:0 bits triggers the update of the internally buffered MUX5 bit. RW 0 MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs is connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Note that the MUX5 bit is located in the ADCSRB register. A write access to the MUX4:0 bits triggers the update of the internally buffered MUX5 bit. RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs is connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Note that the MUX5 bit is located in the ADCSRB register. A write access to the MUX4:0 bits triggers the update of the internally buffered MUX5 bit. RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs is connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Note that the MUX5 bit is located in the ADCSRB register. A write access to the MUX4:0 bits triggers the update of the internally buffered MUX5 bit. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in this register. If differential channels are used, the result is presented in twos complement form. If the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. NA $79 io_analo.bmp N ADCH7 ADC Data Register High Byte These bits represent the result from the conversion. RW 0 ADCH6 ADC Data Register High Byte These bits represent the result from the conversion. RW 0 ADCH5 ADC Data Register High Byte These bits represent the result from the conversion. RW 0 ADCH4 ADC Data Register High Byte These bits represent the result from the conversion. RW 0 ADCH3 ADC Data Register High Byte These bits represent the result from the conversion. RW 0 ADCH2 ADC Data Register High Byte These bits represent the result from the conversion. RW 0 ADCH1 ADC Data Register High Byte These bits represent the result from the conversion. RW 0 ADCH0 ADC Data Register High Byte These bits represent the result from the conversion. RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in this register. If differential channels are used, the result is presented in twos complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. NA $78 io_analo.bmp N ADCL7 ADC Data Register Low Byte These bits represent the result from the conversion. RW 0 ADCL6 ADC Data Register Low Byte These bits represent the result from the conversion. RW 0 ADCL5 ADC Data Register Low Byte These bits represent the result from the conversion. RW 0 ADCL4 ADC Data Register Low Byte These bits represent the result from the conversion. RW 0 ADCL3 ADC Data Register Low Byte These bits represent the result from the conversion. RW 0 ADCL2 ADC Data Register Low Byte These bits represent the result from the conversion. RW 0 ADCL1 ADC Data Register Low Byte These bits represent the result from the conversion. RW 0 ADCL0 ADC Data Register Low Byte These bits represent the result from the conversion. RW 0 ADCSRA The ADC Control and Status Register A NA $7A io_flag.bmp Y ADEN ADC Enable Writing this bit to one enables the ADC. The AVDD supply voltage will also be enabled if not already available. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will include a start-up time to initialize the analog blocks of the ADC. The start-up time is defined by the ADSUT bits of register ADCSRC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. RW 0 ADATE ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. RW 0 ADIF ADC Interrupt Flag This bit is set when an AD conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify- Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the CPU frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the CPU frequency and the input clock to the ADC. RW 1 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the CPU frequency and the input clock to the ADC. RW ANALIG_ADC_PRESCALER 0 ADCSRB The ADC Control and Status Register B NA $7B io_flag.bmp Y AVDDOK AVDD Supply Voltage OK The analog functions of the ADC are powered from the AVDD domain. AVDD is supplied from an internal voltage regulator. Setting the ADEN bit in register ADCSRA will power-up the AVDD domain if not already requested by another functional group of the device. The bit allows the user to monitor (poll) the status of the AVDD domain. A status of 1 indicates that AVDD has been powered-up. R 0 ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. RW 0 REFOK Reference Voltage OK The status of the internal generated reference voltage can be monitored through this bit. Setting the ADEN bit in register ADCSRA will enable the reference voltage for the ADC according to the REFS bits in the ADMUX register. The reference voltage will be available after a start-up delay. A status of 1 of this bit indicates that the internal generated reference voltage is reaching nominal levels. R 0 ACCH Analog Channel Change This bit indicates that a new analog channel has been selected. The MUX bits in ADMUX and ADCSRB have changed. The analog blocks of the ADC will be reset to handle possible new voltage ranges. Such a reset phase is especially important for the gain amplifier. It could be temporarily disabled by a large step of its input common voltage leading to erroneous AD conversion results. The user can force a reset of the analog blocks by setting this bit to 1 independent from requesting a different channel. RW 0 MUX5 Analog Channel and Gain Selection Bits This bit is used together with MUX4:0 in ADMUX to select which combination of the analog inputs are connected to the ADC. If this bit is changed during a conversion, the change will not go in effect until this conversion is complete.Note that the MUX5 bit is internally buffered and a write access to the MUX4:0 bits is required to trigger the update of the MUX5 bit. The MUX4:0 bits are located in the ADMUX register. RW 0 ADTS2 ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an AD conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. RW 0 ADTS1 ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an AD conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. RW 0 ADTS0 ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an AD conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. RW ANALIG_ADC_AUTO_TRIGGER 0 ADCSRC The ADC Control and Status Register C This register defines the track-and-hold time for sampling the analog input voltage of the ADC and it defines the start-up time for the analog blocks based on a number of ADC clock cycles. The ADC clock is generated from the system clock with the ADC prescaler. The bits ADPS2:0 of register ADCSRA set the prescaler ratio. Correct start-up and track-and-hold times are important for precise conversion results. NA $77 io_flag.bmp Y ADTHT1 ADC Track-and-Hold Time These bits define the number of ADC clock cycles for the sampling time of the analog input voltage. RW 0 ADTHT0 ADC Track-and-Hold Time These bits define the number of ADC clock cycles for the sampling time of the analog input voltage. RW ANALOG_ADC_TRACK_AND_HOLD_TIME 1 Res0 Reserved This bit is reserved. RW 0 ADSUT4 ADC Start-up Time These bits define the number of ADC clock cycles for the start-up time of the analog blocks. RW 1 ADSUT3 ADC Start-up Time These bits define the number of ADC clock cycles for the start-up time of the analog blocks. RW 0 ADSUT2 ADC Start-up Time These bits define the number of ADC clock cycles for the start-up time of the analog blocks. RW 1 ADSUT1 ADC Start-up Time These bits define the number of ADC clock cycles for the start-up time of the analog blocks. RW 0 ADSUT0 ADC Start-up Time These bits define the number of ADC clock cycles for the start-up time of the analog blocks. RW ANALOG_ADC_STARTUP_TIME 0 DIDR2 Digital Input Disable Register 2 Reserved for future use. NA $7D io_analo.bmp Y ADC15D Reserved Bits This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero. RW 0 ADC14D Reserved Bits This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero. RW 0 ADC13D Reserved Bits This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero. RW 0 ADC12D Reserved Bits This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero. RW 0 ADC11D Reserved Bits This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero. RW 0 ADC10D Reserved Bits This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero. RW 0 ADC9D Reserved Bits This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero. RW 0 ADC8D Reserved Bits This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero. RW 0 DIDR0 Digital Input Disable Register 0 For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to AVDD/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to this register. NA $7E io_analo.bmp Y ADC7D Disable ADC7:0 Digital Input When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC6D Disable ADC7:0 Digital Input When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC5D Disable ADC7:0 Digital Input When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC4D Disable ADC7:0 Digital Input When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC3D Disable ADC7:0 Digital Input When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC2D Disable ADC7:0 Digital Input When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC1D Disable ADC7:0 Digital Input When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC0D Disable ADC7:0 Digital Input When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 [SPMCSR] io_cpu.bmp AVRSimIOSPM.SimIOSPM The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. SPMCSR Store Program Memory Control Register The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. Note: Only one SPM instruction should be active at any time. $37 $57 io_flag.bmp Y SPMIE SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared. RW 0 RWWSB Read While Write Section Busy When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated. R 0 SIGRD Signature Row Read If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. A SPM instruction within four cycles after SIGRD and SPMEN are set, will have no effect. This operation is reserved for future use and should not be used. RW 0 RWWSRE Read While Write Section Read Enable When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lost. RW 0 BLBSET Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. A LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than "10001", "01001", "00101", "00011" or "00001" in the lower five bits will have no effect. RW 0 [SREG:SPH:SPL:MCUCR:MCUSR:OSCCAL:CLKPR:SMCR:RAMPZ:GPIOR2:GPIOR1:GPIOR0:PRR2:PRR1:PRR0] [SPH:SPL] io_cpu.bmp SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two's complement overflow flag V. See the Instruction Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two's complement overflow flag V supports two's complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. $3E $5E io_sph.bmp N SP15 Stack Pointer High Byte RW 0 SP14 Stack Pointer High Byte RW 0 SP13 Stack Pointer High Byte RW 1 SP12 Stack Pointer High Byte RW 0 SP11 Stack Pointer High Byte RW 0 SP10 Stack Pointer High Byte RW 0 SP9 Stack Pointer High Byte RW 0 SP8 Stack Pointer High Byte RW 1 SP_HIGH_BITF SPL Stack Pointer Low The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. $3D $5D io_sph.bmp N SP7 Stack Pointer Low Byte RW 1 SP6 Stack Pointer Low Byte RW 1 SP5 Stack Pointer Low Byte RW 1 SP4 Stack Pointer Low Byte RW 1 SP3 Stack Pointer Low Byte RW 1 SP2 Stack Pointer Low Byte RW 1 SP1 Stack Pointer Low Byte RW 1 SP0 Stack Pointer Low Byte RW 1 SP_LOW_BITF MCUCR MCU Control Register The MCU Control Register contains control bits for general Microcontroller Unit functions. $35 $55 io_flag.bmp Y JTD JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value. Note that this bit must not be altered when using the On-chip Debug system. RW 0 Res1 Reserved R 0 Res0 Reserved R 0 PUD Pull-up Disable When this bit is written to one, the I/O ports pull-up resistors are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn, PORTxn} = 2'b01). See section "Ports as General Digital I/O" for more details about this feature. RW 0 Res1 Reserved R 0 Res0 Reserved R 0 IVSEL Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section "Memory Programming" for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit (see section "Moving Interrupts Between Application and Boot Section" for details): 1. Write the Interrupt Vector Change Enable (IVCE) bit to one; 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will be automatically disabled while this sequence is executed. Interrupts are disabled in the same cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note that if Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. RW 0 IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts as explained in the IVSEL description. RW 0 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. Note, after power on the bit EXTRF has to be ignored. $34 $54 io_flag.bmp Y Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 JTRF JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. RW 0 WDRF Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. R/W 0 BORF Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. R/W 0 EXTRF External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. R/W 0 PORF Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. R/W 0 OSCCAL Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A preprogrammed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in the section "Electrical Characteristics". Calibration outside that range is not guaranteed. Note that this oscillator is used to time EEPROM and Flash write accesses and these write times will be affected accordingly. The calibration to very high frequencies can cause EEPROM or Flash erase/write failures. The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80. The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. NA $66 io_cpu.bmp Y CAL7 Oscillator Calibration Tuning Value R/W 0 CAL6 Oscillator Calibration Tuning Value R/W 0 CAL5 Oscillator Calibration Tuning Value R/W 0 CAL4 Oscillator Calibration Tuning Value R/W 0 CAL3 Oscillator Calibration Tuning Value R/W 0 CAL2 Oscillator Calibration Tuning Value R/W 0 CAL1 Oscillator Calibration Tuning Value R/W 0 CAL0 Oscillator Calibration Tuning Value R/W 0 OSCCAL_BITF CLKPR Clock Prescale Register NA $61 io_cpu.bmp Y CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. RW 0 Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 CLKPS3 Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in the following table. Note that the factor is different when using the internal 16MHz RC oscillator as the clock source. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is not programmed, the CLKPS bits will be reset to 0000. If CKDIV8 is programmed, CLKPS bits are reset to 0011 giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. RW 0 CLKPS2 Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in the following table. Note that the factor is different when using the internal 16MHz RC oscillator as the clock source. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is not programmed, the CLKPS bits will be reset to 0000. If CKDIV8 is programmed, CLKPS bits are reset to 0011 giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. RW 0 CLKPS1 Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in the following table. Note that the factor is different when using the internal 16MHz RC oscillator as the clock source. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is not programmed, the CLKPS bits will be reset to 0000. If CKDIV8 is programmed, CLKPS bits are reset to 0011 giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. RW 0 CLKPS0 Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in the following table. Note that the factor is different when using the internal 16MHz RC oscillator as the clock source. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is not programmed, the CLKPS bits will be reset to 0000. If CKDIV8 is programmed, CLKPS bits are reset to 0011 giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. RW 0 CPU_CLK_PRESCALE_4_BITS_SMALL_MEGARF SMCR Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. $33 $53 io_cpu.bmp Y Res3 Reserved R 0 Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 SM2 Sleep Mode Select bit 2 These bits select between the five available sleep modes. Standby modes are only recommended for use with external crystals or resonators. RW 0 SM1 Sleep Mode Select bit 1 These bits select between the five available sleep modes. Standby modes are only recommended for use with external crystals or resonators. RW 0 SM0 Sleep Mode Select bit 0 These bits select between the five available sleep modes. Standby modes are only recommended for use with external crystals or resonators. RW CPU_SLEEP_MODE_3BITS 0 SE Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. RW 0 RAMPZ Extended Z-pointer Register for ELPM/SPM For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL. Note that LPM is not affected by the RAMPZ setting. $3B $5B io_cpu.bmp Y Res5 Reserved For compatibility with future devices, be sure to write these bits to zero. RW 0 Res4 Reserved For compatibility with future devices, be sure to write these bits to zero. RW 0 Res3 Reserved For compatibility with future devices, be sure to write these bits to zero. RW 0 Res2 Reserved For compatibility with future devices, be sure to write these bits to zero. RW 0 Res1 Reserved For compatibility with future devices, be sure to write these bits to zero. RW 0 Res0 Reserved For compatibility with future devices, be sure to write these bits to zero. RW 0 RAMPZ1 Extended Z-Pointer Value These two bits represent the MSB's of the Z-Pointer. RW 0 RAMPZ0 Extended Z-Pointer Value These two bits represent the MSB's of the Z-Pointer. RW 0 RAMPZ_BITF GPIOR2 General Purpose I/O Register 2 The three General Purpose I/O Registers can be used for storing any information. $2B $4B io_cpu.bmp Y GPIOR27 General Purpose I/O Register 2 Value RW 0 GPIOR26 General Purpose I/O Register 2 Value RW 0 GPIOR25 General Purpose I/O Register 2 Value RW 0 GPIOR24 General Purpose I/O Register 2 Value RW 0 GPIOR23 General Purpose I/O Register 2 Value RW 0 GPIOR22 General Purpose I/O Register 2 Value RW 0 GPIOR21 General Purpose I/O Register 2 Value RW 0 GPIOR20 General Purpose I/O Register 2 Value RW 0 GPIOR1 General Purpose IO Register 1 The three General Purpose I/O Registers can be used for storing any information. $2A $4A io_cpu.bmp Y GPIOR17 General Purpose I/O Register 1 Value RW 0 GPIOR16 General Purpose I/O Register 1 Value RW 0 GPIOR15 General Purpose I/O Register 1 Value RW 0 GPIOR14 General Purpose I/O Register 1 Value RW 0 GPIOR13 General Purpose I/O Register 1 Value RW 0 GPIOR12 General Purpose I/O Register 1 Value RW 0 GPIOR11 General Purpose I/O Register 1 Value RW 0 GPIOR10 General Purpose I/O Register 1 Value RW 0 GPIOR0 General Purpose IO Register 0 The three General Purpose I/O Registers can be used for storing any information. $1E $3E io_cpu.bmp Y GPIOR07 General Purpose I/O Register 0 Value RW 0 GPIOR06 General Purpose I/O Register 0 Value RW 0 GPIOR05 General Purpose I/O Register 0 Value RW 0 GPIOR04 General Purpose I/O Register 0 Value RW 0 GPIOR03 General Purpose I/O Register 0 Value RW 0 GPIOR02 General Purpose I/O Register 0 Value RW 0 GPIOR01 General Purpose I/O Register 0 Value RW 0 GPIOR00 General Purpose I/O Register 0 Value RW 0 PRR2 Power Reduction Register 2 The Power Reduction Register PRR2 allows to individually disable all four SRAM blocks. Setting any PRRAM3:0 bit to one will completely switch off (disconnect from the power supply) the corresponding SRAM block. This enables the application to disable unused SRAM memory to save power. Every SRAM block can be re-enabled by reseting the appropriate PRRAM3:0 bit. NA $63 io_cpu.bmp Y Res3 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res2 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 PRRAM3 Power Reduction SRAM 3 Setting this bit to one will disable the SRAM block 3. Setting this bit to zero will enable the SRAM block 3. RW 0 PRRAM2 Power Reduction SRAM 2 Setting this bit to one will disable the SRAM block 2. Setting this bit to zero will enable the SRAM block 2. RW 0 PRRAM1 Power Reduction SRAM 1 Setting this bit to one will disable the SRAM block 1. Setting this bit to zero will enable the SRAM block 1. RW 0 PRRAM0 Power Reduction SRAM 0 Setting this bit to one will disable the SRAM block 0. Setting this bit to zero will enable the SRAM block 0. RW 0 PRR1 Power Reduction Register 1 NA $65 io_cpu.bmp Y Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 PRTRX24 Power Reduction Transceiver Writing a logic one to this bit shuts down the transceiver (disconnect from the power supply). In power-down and power-save modes the power-chain will be disabled when this bit is one. Writing a logic zero to this bit will re-enable the transceiver. RW 0 PRTIM5 Power Reduction Timer/Counter5 Writing a logic one to this bit shuts down the Timer/Counter5 module. When the Timer/Counter5 is enabled, operation will continue like before the shutdown. RW 0 PRTIM4 Power Reduction Timer/Counter4 Writing a logic one to this bit shuts down the Timer/Counter4 module. When the Timer/Counter4 is enabled, operation will continue like before the shutdown. RW 0 PRTIM3 Power Reduction Timer/Counter3 Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is enabled, operation will continue like before the shutdown. RW 0 PRUSART3 Reserved This bit is reserved for future use. It has currently no associated function. RW 0 PRUSART2 Reserved This bit is reserved for future use. It has currently no associated function. RW 0 PRUSART1 Power Reduction USART1 Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be reinitialized to ensure proper operation. RW 0 PRR0 Power Reduction Register0 NA $64 io_cpu.bmp Y PRTWI Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation. R/W 0 PRTIM2 Power Reduction Timer/Counter2 Writing a logic one to this bit shuts down the Timer/Counter2 module. When the Timer/Counter2 is enabled, operation will continue like before the shutdown. R/W 0 PRTIM0 Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. R/W 0 PRPGA Power Reduction PGA Writing a logic one to this bit reduced the power consumption of the programmable gain amplifier. The block is not turned off. Only the current levels in the amplifiers are reduced. Reducing the PGA current levels is only recommended for slow ADC clock frequencies. A new ADC conversion using the PGA should be delayed by a default start-up time after changing (setting or resetting) this bit. R/W 0 PRTIM1 Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. R/W 0 PRSPI Power Reduction Serial Peripheral Interface Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation. R/W 0 PRUSART0 Power Reduction USART Writing a logic one to this bit shuts down the USART0 by stopping the clock to the module. When waking up the USART0 again, the USART0 should be reinitialized to ensure proper operation. R/W 0 PRADC Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled (reset ADEN bit in register ADCSRA) before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. R/W 0 [NEMCR:BGCR] io_flash.bmp NEMCR Flash Extended-Mode Control-Register The Flash Extended-Mode Control-Register handles the extended address-mode of the extra rows. NA $75 io_flash.bmp Y ENEAM Enable Extended Address Mode for Extra Rows When active high, the extended address mode of the extra rows is enabled. The address is decoded from bits AEAM1:0 of this register. RW 0 AEAM1 Address for Extended Address Mode of Extra Rows These bits are only used when bit ENEAM of this register is set high. Then AEAM1:0 are used to decode the addresses of the extra rows. A value of 0 decodes the default factory row that is also accessible when the extended address mode is deactivated. RW 0 AEAM0 Address for Extended Address Mode of Extra Rows These bits are only used when bit ENEAM of this register is set high. Then AEAM1:0 are used to decode the addresses of the extra rows. A value of 0 decodes the default factory row that is also accessible when the extended address mode is deactivated. RW 0 NEMCR_ADDRESS_BITF BGCR Reference Voltage Calibration Register This register contains the calibration values of the reference voltage of the ADC. The values are loaded from the fuse memory after power-up. They can be corrected by the application software e.g. to compensate for temperature changes. The internal 1.6V reference voltage is calibrated and has therefore the highest accuracy compared to the 1.5V or AVDD reference. NA $67 io_flash.bmp Y Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 BGCAL_FINE3 Fine Calibration Bits These bits allow the calibration of the AREF voltage with a resolution of 2mV. RW 0 BGCAL_FINE2 Fine Calibration Bits These bits allow the calibration of the AREF voltage with a resolution of 2mV. RW 0 BGCAL_FINE1 Fine Calibration Bits These bits allow the calibration of the AREF voltage with a resolution of 2mV. RW 0 BGCAL_FINE0 Fine Calibration Bits These bits allow the calibration of the AREF voltage with a resolution of 2mV. RW 0 BGCAL_FINE_BITF BGCAL2 Coarse Calibration Bits These bits allow the calibration of the AREF voltage with a resolution of 10mV. RW 0 BGCAL1 Coarse Calibration Bits These bits allow the calibration of the AREF voltage with a resolution of 10mV. RW 0 BGCAL0 Coarse Calibration Bits These bits allow the calibration of the AREF voltage with a resolution of 10mV. RW 0 BGCAL_BITF [TRXPR:DRTRAM0:DRTRAM1:DRTRAM2:DRTRAM3:LLDRL:LLDRH:LLCR:DPDS0:DPDS1:MCUCR] io_pwrctrl.bmp TRXPR Transceiver Pin Register The register TRXPR allows to control basic actions of the radio transceiver like reset or state transitions. The register bit functionality is inherited from the external pins of the stand-alone radio transceiver. NA $139 io_flag.bmp Y Res3 Reserved R 0 Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 SLPTR Multi-purpose Transceiver Control Bit The bit SLPTR is a multi-functional bit to control transceiver state transitions. Dependent on the radio transceiver state, a rising edge of bit SLPTR causes the following state transitions: TRX_OFF => SLEEP (level sensitive), PLL_ON => BUSY_TX. Whereas the falling edge of bit SLPTR causes the following state transition: SLEEP => TRX_OFF (level sensitive). When the radio transceiver is in TRX_OFF state the microcontroller forces the transceiver to SLEEP by setting SLPTR = H. The Transceiver awakes when the microcontroller releases the bit SLPTR. In states PLL_ON and TX_ARET_ON, bit SLPTR is used as trigger input to initiate a TX transaction. Here SLPTR is sensitive on rising edge only. After initiating a state change by a rising edge at Bit SLPTR in radio transceiver states TRX_OFF, RX_ON or RX_AACK_ON, the radio transceiver remains in the new state as long as the pin is logical high and returns to the preceding state with the falling edge. RW 0 TRXRST Force Transceiver Reset The RESET state is used to set back the state machine and to reset all registers of the transceiver to their default values. A reset forces the radio transceiver into the TRX_OFF state and resets all transceiver register to their default values. A reset is initiated with bit TRXRST = H. The bit is cleared automatically During transceiver reset the microcontroller has to set the radio transceiver control bit SLPTR to the default value. RW 0 DRTRAM0 Data Retention Configuration Register of SRAM 0 The DRTRAM0 register controls the behavior of SRAM block 0 in the power-states "power-save" and "power-down". To prevent any data loss the SRAM will not completely disconnected from the power supply. Instead the SRAM supply voltage can be reduced to a save level thus providing data retention and low leakage current. NA $135 io_flag.bmp Y Res1 Reserved R 0 Res0 Reserved R 0 DRTSWOK DRT Switch OK This bit indicates the status of the SRAM power-switch. A logical one indicates that the SRAM supply voltage is fully available and the memory may be accessed normally. R 0 ENDRT Enable SRAM Data Retention During the power-states "power-down" and "power-save" each SRAM block will either be switched off or provides data retention of its memory content. This bit must set to one if data retention mode should be used. Otherwise the SRAM is switched off (disconnected from the power supply) and all its data are lost. RW 0 DRTRAM1 Data Retention Configuration Register of SRAM 1 The DRTRAM1 register controls the behavior of SRAM block 1 in the power-states "power-save" and "power-down". To prevent any data loss the SRAM will not completely disconnected from the power supply. Instead the SRAM supply voltage can be reduced to a save level thus providing data retention and low leakage current. NA $134 io_flag.bmp Y Res1 Reserved R 0 Res0 Reserved R 0 DRTSWOK DRT Switch OK This bit indicates the status of the SRAM power-switch. A logical one indicates that the SRAM supply voltage is fully available and the memory may be accessed normally. R 0 ENDRT Enable SRAM Data Retention During the power-states "power-down" and "power-save" each SRAM block will either be switched off or provides data retention of its memory content. This bit must set to one if data retention mode should be used. Otherwise the SRAM is switched off (disconnected from the power supply) and all its data are lost. RW 0 DRTRAM2 Data Retention Configuration Register of SRAM 2 The DRTRAM2 register controls the behavior of SRAM block 2 in the power-states "power-save" and "power-down". To prevent any data loss the SRAM will not completely disconnected from the power supply. Instead the SRAM supply voltage can be reduced to a save level thus providing data retention and low leakage current. NA $133 io_flag.bmp Y Res Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 DRTSWOK DRT Switch OK This bit indicates the status of the SRAM power-switch. A logical one indicates that the SRAM supply voltage is fully available and the memory may be accessed normally. R 0 ENDRT Enable SRAM Data Retention During the power-states "power-down" and "power-save" each SRAM block will either be switched off or provides data retention of its memory content. This bit must set to one if data retention mode should be used. Otherwise the SRAM is switched off (disconnected from the power supply) and all its data are lost. RW 0 DRTRAM3 Data Retention Configuration Register of SRAM 3 The DRTRAM3 register controls the behavior of SRAM block 3 in the power-states "power-save" and "power-down". To prevent any data loss the SRAM will not completely disconnected from the power supply. Instead the SRAM supply voltage can be reduced to a save level thus providing data retention and low leakage current. NA $132 io_flag.bmp Y Res1 Reserved R 0 Res0 Reserved R 0 DRTSWOK DRT Switch OK This bit indicates the status of the SRAM power-switch. A logical one indicates that the SRAM supply voltage is fully available and the memory may be accessed normally. R 0 ENDRT Enable SRAM Data Retention During the power-states "power-down" and "power-save" each SRAM block will either be switched off or provides data retention of its memory content. This bit must set to one if data retention mode should be used. Otherwise the SRAM is switched off (disconnected from the power supply) and all its data are lost. RW 0 LLDRL Low Leakage Voltage Regulator Data Register (Low-Byte) The low-byte of the calibration data can be accessed through this register. Write access is only enabled when the bit LLENCAL of the LLCR register is 0. Then the data bits LLDRL3:0 directly control the output voltage of the low-leakage voltage regulator. Higher numbers generate lower voltages. The contents of this register is meaningless when the bit LLSHORT of the LLCR register is 1. If the bit LLENCAL is 1 then the results of the automatic calibration are stored. NA $130 io_flag.bmp Y Res3 Reserved These bits are reserved for future use. R 0 Res2 Reserved These bits are reserved for future use. R 0 Res1 Reserved These bits are reserved for future use. R 0 Res0 Reserved These bits are reserved for future use. R 0 LLDRL3 Low-Byte Data Register Bits Value of the low-byte calibration result RW 0 LLDRL2 Low-Byte Data Register Bits Value of the low-byte calibration result RW 0 LLDRL1 Low-Byte Data Register Bits Value of the low-byte calibration result RW 0 LLDRL0 Low-Byte Data Register Bits Value of the low-byte calibration result RW 0 LLDRL_VALUE_BITF LLDRH Low Leakage Voltage Regulator Data Register (High-Byte) The high-byte of the calibration data can be accessed through this register. Write access is only enabled when the bit LLENCAL of the LLCR register is 0. Then the data bits LLDRH4:0 directly control the output voltage of the low-leakage voltage regulator. Higher numbers generate lower voltages. If the bit LLENCAL is 1 then the results of the automatic calibration are stored. NA $131 io_flag.bmp Y Res2 Reserved These bits are reserved for future use. R 0 Res1 Reserved These bits are reserved for future use. R 0 Res0 Reserved These bits are reserved for future use. R 0 LLDRH4 High-Byte Data Register Bits Value of the high-byte calibration result RW 0 LLDRH3 High-Byte Data Register Bits Value of the high-byte calibration result RW 0 LLDRH2 High-Byte Data Register Bits Value of the high-byte calibration result RW 0 LLDRH1 High-Byte Data Register Bits Value of the high-byte calibration result RW 0 LLDRH0 High-Byte Data Register Bits Value of the high-byte calibration result RW 0 LLDRH_VALUE_BITF LLCR Low Leakage Voltage Regulator Control Register This register allows to monitor and to control the calibration process of the low-leakage voltage regulator. The automatic calibration is the normal operation mode. However, certain circumstances may require to disable this automatic process for instance to save power-up time. The results of the automatic calibration can also be modified when required by the application for instance to get a higher or lower output voltage. NA $12F io_flag.bmp Y Res1 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 Res0 Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. R 0 LLDONE Calibration Done This bit indicates the last state of the calibration algorithm. The data register contents is updated with new calibration data after the bit changed to 1. The bit will only be high for one 64kHz clock period, because a new calibration loop is started automatically. R 0 LLCOMP Comparator Output This bit indicates the output state of the comparator of the low-leakage voltage regulator. In this way the calibration progress can be directly monitored for debug purposes. The state of the bit changes at most every 64kHz clock period. R 0 LLCAL Calibration Active This bit indicates that the automatic calibration is in progress. The analog part of the calibration circuit is powered up if the bit is 1. R 0 LLTCO Temperature Coefficient of Current Source This bit shows the status of the selection of the temperature coefficient. The state of the bit is updated in the course of the automatic calibration. A valid value is present after the LLDONE bit is 1 for the first time. Write access is only enabled when the automatic calibration is turned off (LLENCAL is 0). This bit should not be changed without further information. RW 0 LLSHORT Short Lower Calibration Circuit This bit shows the status of the short switch for the lower calibration circuit. The state of the bit is updated in the course of the automatic calibration. A valid value is present after the LLDONE bit is 1 for the first time. If this bit is set to 1 register LLDRL has no function. Write access is only possible when the automatic calibration is turned off (LLENCAL is 0). This bit should not be changed without further information. RW 0 LLENCAL Enable Automatic Calibration This bit enables the automatic calibration. The automatic calibration runs if the state of the bit is 1. Write access to the two data register and the bits LLSHORT and LLTCO is then denied. If the state of LLENCAL is 0 then the calibration algorithm is stopped and the output voltage of the low-leakage voltage regulator is defined by the values in the two data register LLDRL and LLDRH and by the bits LLSHORT and LLTCO. RW 1 DPDS0 Port Driver Strength Register 0 The output driver strength can be set individually for each digital I/O port. The following tables show output current levels for a typical supply voltage of DEVDD = 3.3V. Refer to section "Electrical Characteristics" for details. NA $136 io_flag.bmp Y PFDRV1 Driver Strength Port F RW 0 PFDRV0 Driver Strength Port F RW 0 PAD_IO_bitf PEDRV1 Driver Strength Port E RW 0 PEDRV0 Driver Strength Port E RW 0 PAD_IO_bitf PDDRV1 Driver Strength Port D RW 0 PDDRV0 Driver Strength Port D RW 0 PAD_IO_bitf PBDRV1 Driver Strength Port B RW 0 PBDRV0 Driver Strength Port B RW 0 PAD_IO_bitf DPDS1 Port Driver Strength Register 1 The output driver strength can be set individually for each digital I/O port. The following table shows output current levels for a typical supply voltage of DEVDD = 3.3V. Refer to section "Electrical Characteristics" for details. NA $137 io_flag.bmp Y Res5 Reserved R 0 Res4 Reserved R 0 Res3 Reserved R 0 Res2 Reserved R 0 Res1 Reserved R 0 Res0 Reserved R 0 PGDRV1 Driver Strength Port G RW 0 PGDRV0 Driver Strength Port G RW 0 PAD_IO_bitf MCUCR MCU Control Register The MCU Control Register contains control bits of the general Microcontroller Unit functions. $35 $55 io_flag.bmp Y PUD Pull-up Disable When this bit is written to one, the I/O ports pull-up resistors are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn, PORTxn} = 2'b01). See section "Ports as General Digital I/O" for more details about this feature. RW 0 [UCSR0A:UCSR0B:UCSR0C] io_com.bmp The Universal Synchronous and Asynchronous Serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the following features: Full Duplex, Three-wire Synchronous Data Transfer; Master Operation; Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3); LSB First or MSB First Data Transfer (Configurable Data Order); Queued Operation (Double Buffered); High Resolution Baud Rate Generator; High Speed Operation (fXCKmax = fCK/2); Flexible Interrupt Generation. UCSR0A USART0 MSPIM Control and Status Register A NA $C0 io_flag.bmp Y RXC0 USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXC0 bit will become zero. The RXC0 Flag can be used to generate a Receive Complete interrupt (see description of the RXCIE0 bit). R 0 TXC0 USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR0). The TXC0 Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC0 Flag can generate a Transmit Complete interrupt (see description of the TXCIE0 bit). RW 0 UDRE0 USART Data Register Empty The UDRE0 Flag indicates if the transmit buffer (UDR0) is ready to receive new data. If UDRE0 is one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag can generate a Data Register Empty interrupt (see description of the UDRIE0 bit). UDRE0 is set after a reset to indicate that the Transmitter is ready. R 0 UCSR0B USART0 MSPIM Control and Status Register B NA $C1 io_flag.bmp Y RXCIE0 RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC0 Flag. A USART Receive Complete interrupt will be generated only if the RXCIE0 bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC0 bit in UCSR0A is set. RW 0 TXCIE0 TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC0 Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE0 bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC0 bit in UCSR0A is set. RW 0 UDRIE0 USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Empty interrupt will be generated only if the UDRIE0 bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE0 bit in UCSR0A is set. RW 1 RXEN0 Receiver Enable Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override normal port operation for the RxD0 pin when enabled. Disabling the Receiver will flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXEN0=1 and TXEN0=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported. RW 0 TXEN0 Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD0 pin when enabled. The disabling of the Transmitter (writing TXEN0 to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD0 port. RW 0 UCSR0C USART0 MSPIM Control and Status Register C NA $C2 io_flag.bmp Y UDORD0 UCSZ01 Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to section "Frame Formats" for details. RW 1 UCPHA0 UCSZ00 Clock Phase The UCPHA0 bit setting determines if data is sampled on the leading (first) or tailing (last) edge of XCK0. Refer to the section "SPI Data Modes and Timing" for details. RW 1 UCPOL0 Clock Polarity The UCPOL0 bit sets the polarity of the XCK0 clock. The combination of the UCPOL0 and UCPHA0 bit settings determine the timing of the data transfer. Refer to the section "SPI Data Modes and Timing" for details. RW 0 [UCSR1A:UCSR1B:UCSR1C] io_com.bmp The Universal Synchronous and Asynchronous Serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the following features: Full Duplex, Three-wire Synchronous Data Transfer; Master Operation; Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3); LSB First or MSB First Data Transfer (Configurable Data Order); Queued Operation (Double Buffered); High Resolution Baud Rate Generator; High Speed Operation (fXCKmax = fCK/2); Flexible Interrupt Generation. UCSR1A USART1 MSPIM Control and Status Register A NA $C8 io_flag.bmp Y RXC1 USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXC1 bit will become zero. The RXC1 Flag can be used to generate a Receive Complete interrupt (see description of the RXCIE1 bit). R 0 TXC1 USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR1). The TXC1 Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC1 Flag can generate a Transmit Complete interrupt (see description of the TXCIE1 bit). RW 0 UDRE1 USART Data Register Empty The UDRE1 Flag indicates if the transmit buffer (UDR1) is ready to receive new data. If UDRE1 is one, the buffer is empty, and therefore ready to be written. The UDRE1 Flag can generate a Data Register Empty interrupt (see description of the UDRIE1 bit). UDRE1 is set after a reset to indicate that the Transmitter is ready. R 0 UCSR1B USART1 MSPIM Control and Status Register B NA $C9 io_flag.bmp Y RXCIE1 RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC1 Flag. A USART Receive Complete interrupt will be generated only if the RXCIE1 bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC1 bit in UCSR1A is set. RW 0 TXCIE1 TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC1 Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE1 bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC1 bit in UCSR1A is set. RW 0 UDRIE1 USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE1 Flag. A Data Register Empty interrupt will be generated only if the UDRIE1 bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE1 bit in UCSR1A is set. RW 1 RXEN1 Receiver Enable Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override normal port operation for the RxD1 pin when enabled. Disabling the Receiver will flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXEN1=1 and TXEN1=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported. RW 0 TXEN1 Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD1 pin when enabled. The disabling of the Transmitter (writing TXEN1 to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD1 port. RW 0 UCSR1C USART1 MSPIM Control and Status Register C NA $CA io_flag.bmp Y UDORD1 UCSZ11 Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to section "Frame Formats" for details. RW 1 UCPHA1 UCSZ10 Clock Phase The UCPHA1 bit setting determines if data is sampled on the leading (first) or tailing (last) edge of XCK1. Refer to the section "SPI Data Modes and Timing" for details. RW 1 UCPOL1 Clock Polarity The UCPOL1 bit sets the polarity of the XCK1 clock. The combination of the UCPOL1 and UCPHA1 bit settings determine the timing of the data transfer. Refer to the section "SPI Data Modes and Timing" for details. RW 0 [ICE50:SIMULATOR:JTAGICEmkII:STK500_2:AVRISPmkII:AVRDragon:STK600:AVRONE] 0x05 0x0F 0x0F 0x0F 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x0F 0x0F 0x0F 0x15 0x14 0x14 0x000021FF 0x00000000 0x00000000 0x00000000 0x00000FFF 0x0001FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x000021FF 0x0000FFFF 0x00000FFF 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x000001FF 0x0000FFFF 0x00000000 0x00000000 0x00000000 0x00000FFF 0x0001FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x00000FFF 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x000001FF 0x000021FF 0x00000000 0x00000000 0x00000000 0x00000FFF 0x0001FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x00000FFF 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x0000FFFF 0x99 0xff 0x62 0xff 0x66 0xC7 AT86RF235.bin 0x02 0x00 1000000 40000000 7 2 ; INTOSC = 1, INTRC=2;EXTCLK=4 1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 0 0x01 0x00 0x80 0x00 0x01 8 0x00000600 0x00000600 Boot Size 512 Words, 4 pages, $FE00-$FFFF, Boot reset $FE00 0x00000600 0x00000400 Boot Size 1024 Words, 8 pages, $FC00-$FFFF, Boot reset $FC00 0x00000600 0x00000200 Boot Size 2048 Words, 16 pages, $F800-$FFFF, Boot reset $F800 0x00000600 0x00000000 Boot Size 4096 Words, 32 pages, $F000-$FFFF, Boot reset $F000 0x00000031 0x00000000 258 CK, 4.1 ms 0x00000031 0x00000010 258 CK, 65 ms 0x00000031 0x00000020 1K CK 0x00000031 0x00000030 1K CK, 4.1 ms 0x00000031 0x00000001 1K CK, 65 ms 0x00000031 0x00000011 16K CK 0x00000031 0x00000021 16K CK, 4.1 ms 0x00000031 0x00000031 16K CK, 65 ms 0x00000030 0x00000000 6 CK,14 CK 0x00000030 0x00000010 6 CK, 14 CK + 4.1ms 0x00000030 0x00000020 6 CK, 65 ms 0x00000030 0x00000000 6 CK, 14 CK 0x00000030 0x00000010 6 CK, 14 CK + 4.1ms 0x00000030 0x00000020 6 CK, 14 CK + 65 ms 0x0000000e 0x0000000e 0x0000000f 0x00000002 8.0 0x0000000f 0x00000000 0x00000100 0x00000100 Application reset, address $0 0x00000100 0x00000000 Boot loader reset 0x0c000000 0x0c000000 No restrictions for SPM or (E)LPM 0x0c000000 0x08000000 No write to the Application section 0x0c000000 0x00000000 No write to Application section, No read from the Application section 0x0c000000 0x04000000 No read from the Application section 0x30000000 0x30000000 No restrictions for SPM or (E)LPM 0x30000000 0x20000000 No write to the Boot Loader section 0x30000000 0x00000000 No write to Boot Loader section, No read from the Boot Loader section 0x30000000 0x10000000 No read from the Boot Loader section 0x00001000 0x00000000 Watchdog always ON 0x00001000 0x00001000 Watchdog disabled 8 0x00000080 0x00000000 CKDIV8 Fuse 0x00000080 0x00000080 CKDIV8 Fuse 0x00000040 0x00000000 CKOUT Fuse 0x00000040 0x00000040 CKOUT Fuse 0x00070000 0x00070000 BOD disabled 0x00070000 0x00060000 BOD enabled, 1.8 V 0x00070000 0x00050000 BOD enabled, 2.7 V 0x00070000 0x00040000 BOD enabled, 4.0 V AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x3c 0 30 AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x12 0x48 0x01 0x1B 0x01 0x4b 0x03 0xff AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x14 0x48 0x02 0x1B 0x02 0xe3 0xff 0x4c AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x16 0x48 0x04 0x1B 0x04 0xe6 0xff 0x4d AVRSimIOExtInterrupt.SimIOExtInterrupt 0x02 0x1d 0x01 0x1c 0x01 0x09 0x01 0x49 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x04 0x1d 0x02 0x1c 0x02 0x09 0x02 0x49 0x0c AVRSimIOExtInterrupt.SimIOExtInterrupt 0x06 0x1d 0x04 0x1c 0x04 0x09 0x04 0x49 0x30 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x08 0x1d 0x08 0x1c 0x08 0x09 0x08 0x49 0xc0 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0a 0x1d 0x10 0x1c 0x10 0x0c 0x10 0x4a 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0c 0x1d 0x20 0x1c 0x20 0x0c 0x20 0x4a 0x0c AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0e 0x1d 0x40 0x1c 0x40 0x0c 0x40 0x4a 0x30 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x10 0x1d 0x80 0x1c 0x80 0x0c 0x80 0x4a 0xc0 AvrSimIOtim8pwmsync2.tim8pwmsync2 0x2A 0x2C 0x2E PORTB 7 PORTG 5 AvrMasterTimer.MasterTimer 0x20 0x22 0x24 0x26 0x28 0x09 0x40 0x09 0x10 0x05 0x20 0x05 0x40 0x05 0x80 TIFR1/OCF1A TIFR1/OCF1B TIFR1/OCF1C 1:8:64:256:1024 0x23 0x01 AvrMasterTimer.MasterTimer 0x1a 0x1c 0x1e PORTB 4 1:8:64:256:1024 AvrMasterTimer.MasterTimer 0x3E 0x40 0x42 0x44 0x46 0x0C 0x40 0x0C 0x80 0x0e 0x08 0x0e 0x10 0x0e 0x20 TIFR3/OCF3A TIFR3/OCF3B TIFR3/OCF3C 1:8:64:256:1024 0x23 0x01 AvrMasterTimer.MasterTimer 0x54 0x56 0x58 0x5a TIFR4/OCF4A TIFR4/OCF4B TIFR4/OCF4C 1:8:64:256:1024 0x23 0x01 AvrMasterTimer.MasterTimer 0x5e 0x60 0x62 0x64 TIFR5/OCF5A TIFR5/OCF5B TIFR5/OCF5C 1:8:64:256:1024 0x23 0x01 AVRSimIOSPM.SimIOSPM 0x50 AVRSimIOSpi.SimIOSpi 0x30 0x03 0x02 0x03 0x08 0x03 0x04 0x03 0x04 0x01 AVRSimIOUsart.SimIOUsart 0x32 0x36 0x34 0x0c 0x02 0x0c 0x01 AVRSimIOUsart.SimIOUsart 0x48 0x4C 0x4A 0x09 0x08 0x09 0x04 AVRSimAC.SimIOAC 0x38 AVRSimADC.SimADC 0x3A AvrSimTWI.SimTWI 0x4E AvrMasterTimer.MasterTimer 0 16384:32768:65536:131072:262144:524288:1048576:2097152 0xFF 0xff 0xFF 0xFF 0x0A70103F JTAG 0xFF,0xFF,0xFF,0xF9,0xFF,0x3D,0xB9,0xF8 0xFF,0xFF,0x1F,0xE0,0xFF,0x1D,0xA9,0xF8 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0xFB,0xFF,0xBF,0xFF,0xF7,0x3F,0xF7,0x3F,0xF7,0x3F,0x5F,0x3F,0x77,0x77,0x03,0xF0,0xFF,0xFF,0xFF,0x01,0x00,0x00,0x00,0x00,0xF7,0xBF,0xFF,0xFA,0xFE,0xFF,0xA7,0xFF,0xFF,0xFF,0xEF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF 0xFB,0xFF,0xBF,0xFF,0xB7,0x3F,0xB7,0x3F,0xB7,0x3F,0x5F,0x3F,0x77,0x77,0x03,0xB0,0xFF,0xE1,0xFF,0x01,0x00,0x00,0x00,0x00,0xB7,0xBF,0xFF,0xDA,0x3C,0xFF,0xA7,0x0F,0xFF,0xFF,0xE8,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x31 0x57 0x0100 0x0008 0xFE00 0x01FF 0x0000,32 0x0020,64 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0 0 0x00 0x00 0x00 0x01 0x3F 1 0 0 1 200 100 25 32 0 3 0x53 1 1 55 1 0x41 256 10 0x40 0x4C 0x00 0x00 0x00 0x41 8 10 0xC1 0xC2 0x00 0x00 0x00 256 256 4 4 4 4 0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00 100 0 5 1 15 1 0 15 15 0 10 5 0x01 256 256 5 0x07 256 256 0 5 0 5 200 100 25 32 0 3 0x53 1 1 55 1 0x41 256 6 0x40 0x4C 0x00 0x00 0x00 0x41 8 10 0xC1 0xC2 0x00 0x00 0x00 256 256 4 4 4 4 0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00 100 0 6 0 0 0 0 15 15 0 10 5 0x01 256 256 5 0x07 256 256 0 5 0 5 0x0A70103F JTAG