[PROGRAMMING:MEMORY:LOCKBIT:FUSE:ADMIN:IO_MODULE:ICE_SETTINGS] 1 0 AVRSimMemory8bit.SimMemory8bit 8192 0 0x18 0x38 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x17 0x37 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x16 0x36 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 [LB1 = 1 : LB2 = 1 : LB3 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1 : LB3 = 1] MOVC disabled. [LB1 = 0 : LB2 = 0 : LB3 = 1] Same as previous, but verify is also disabled. [LB1 = 0 : LB2 = 0 : LB3 = 0] Same as previous, but external execution is also disabled. 4 3 0x1C 0x00 Mode 1: No memory lock features enabled 0x1C 0x04 Mode 2: MOVC disabled 0x1C 0x0c Mode 3: Verify disabled 0x1C 0x1C Mode 4: External execution disabled LB1 Lockbit LB2 Lockbit LB3 Lockbit [LOW] AT89S52 4MHz 1 RELEASED Y $1E $52 $06 [PORTA] [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register 0x18 0x38 io_port.bmp N PORTA7 Port A Data Register bit 7 RW 0 PORTA6 Port A Data Register bit 6 RW 0 PORTA5 Port A Data Register bit 5 RW 0 PORTA4 Port A Data Register bit 4 RW 0 PORTA3 Port A Data Register bit 3 RW 0 PORTA2 Port A Data Register bit 2 RW 0 PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 DDRA Port A Data Direction Register 0x17 0x37 io_flag.bmp N DDA7 Data Direction Register, Port A, bit 7 RW 0 DDA6 Data Direction Register, Port A, bit 6 RW 0 DDA5 Data Direction Register, Port A, bit 5 RW 0 DDA4 Data Direction Register, Port A, bit 4 RW 0 DDA3 Data Direction Register, Port A, bit 3 RW 0 DDA2 Data Direction Register, Port A, bit 2 RW 0 DDA1 Data Direction Register, Port A, bit 1 RW 0 DDA0 Data Direction Register, Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. 0x16 0x36 io_port.bmp N PINA7 Input Pins, Port A bit 7 RW Hi-Z PINA6 Input Pins, Port A bit 6 RW Hi-Z PINA5 Input Pins, Port A bit 5 RW Hi-Z PINA4 Input Pins, Port A bit 4 RW Hi-Z PINA3 Input Pins, Port A bit 3 RW Hi-Z PINA2 Input Pins, Port A bit 2 RW Hi-Z PINA1 Input Pins, Port A bit 1 RW Hi-Z PINA0 Input Pins, Port A bit 0 RW Hi-Z [STK500:STK500_2:AVRISPmkII] 0xE1 0 0 0 0x00 0x00 0x00 0 1 200 100 25 32 0 4 0x69 1 1 250 0 0x02 256 10 0x40 0x00 0x20 0x00 0x00 0x02 4 6 0xC0 0x00 0xA0 0x00 0xFF 256 256 4 4 4 4