[ADMIN:CORE:INTERRUPT_VECTOR:MEMORY:PACKAGE:FUSE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS] AT86RF401 8MHZ 201 RELEASED $1E $91 $81 V2 [lpm rd,z+] [sleep] [] 32 $00 $1B $1A $1D $1C $1F $1E 3 $000 RESETB Hardware pin, Watchdog or Button Reset $002 TXDONE Transmission Done, Bit Timer Flag 2 Interrupt $004 TXEMPTY Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt AVRSimMemory8bit.SimMemory8bit 2048 128 128 $60 0 NA $00 $3F $20 $5F $3F $5F 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $3E $5E 0x01 0x02 0x04 $3D $5D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $35 $55 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $34 $54 0x01 0x02 0x04 0x08 0x10 0x20 $33 $53 0x01 0x02 0x04 0x08 0x10 0x20 0x40 $32 $52 0x01 0x02 0x04 0x08 0x10 0x20 $31 $51 0x01 0x02 0x04 0x08 0x10 0x20 $30 $50 0x01 0x02 0x04 0x08 0x10 0x20 $22 $42 0x01 0x02 0x04 0x08 0x10 $21 $41 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $20 $40 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1E $3E 0x01 0x02 0x04 0x08 0x10 0x20 0x40 $1D $3D 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $1C $3C 0x01 0x02 0x04 0x08 $17 $37 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 $16 $36 0x01 0x02 0x04 0x08 0x10 0x40 0x80 $14 $34 0x01 0x02 0x04 0x08 0x10 0x20 $12 $32 0x04 0x10 0x20 0x40 $10 $30 0x01 0x02 0x04 0x08 0x10 [TSSOP] 20 [ANTB] [LOOPFIL] [L1] [L2] [RESETB] [N/C] [IO0:SDI] [IO1:SDO] [IO2:SCK] [XTAL:CLK] [XTALB] [IO3] [IO4] [IO5] [DGND] [AGND] [DVDD] [AVDD] [CFIL] [ANT] [LOW] 0x00 0 0 [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x06 0x06 Mode 1: No memory lock features enabled 0x06 0x04 Mode 2: Further programming disabled 0x06 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit [RF_CONTROL:EEPROM:WATCHDOG:TIMER_COUNTER_0:PORT:CPU] [LOCKDET1:LOCKDET2:TX_CNTL:PWR_ATTEN:VCOTUNE] io_cpu.bmp LOCKDET1 Lock Detector Configuration Register 1 $10 $30 io_flag.bmp Y UPOK Unlock Conuter Control RW 0 ENKO Enable Key On Bit RW 0 BOD Black Out Disable RW 0 CS1 Cycle Slip Counter bit 1 RW 0 CS0 Cycle Slip Counter bit 0 RW 0 LOCKDET1 Lock Detector Configuration register 2 $17 $37 io_flag.bmp Y EUD Enable Unlock Detect RW 0 LAT Lock Always True RW 0 ULC2 Unlock Count bit 2 RW 0 ULC1 Unlock Count bit 1 RW 0 ULC0 Unlock Count bit 0 RW 0 LC2 Lock Count bit 2 RW 0 LC1 Lock Count bit 1 RW 0 LC0 Lock Count bit 0 RW 0 TX_CNTL Transmit Control Register $12 $32 io_flag.bmp Y FSK FSK Mode RW 0 TXE Transmitter Enable RW 0 TXK Transmitter Key RW 0 LOC PLL Lock RW 0 PWR_ATTEN Power Attenuation Control Register This register is used to select the power attenuation level of the device. $14 $34 io_flag.bmp Y PCC2 Power Control Coarse bit 2 RW 0 PCC1 Power Control Coarse bit 1 RW 0 PCC0 Power Control Coarse bit 0 RW 0 PCF2 Power Control Fine bit 2 RW 0 PCF1 Power Control Fine bit 1 RW 0 PCF0 Power Control Fine bit 0 RW 0 VCOTUNE VCO Tuning Register $16 $36 io_flag.bmp Y VCOVDET1 VCO Voltage Detector bit 1 RW 0 VCOVDET0 VCO Voltage Detector bit 0 RW 0 VCOTUNE4 VCO Tuning Register bit 4 RW 0 VCOTUNE3 VCO Tuning Register bit 3 RW 0 VCOTUNE2 VCO Tuning Register bit 2 RW 0 VCOTUNE1 VCO Tuning Register bit 1 RW 0 VCOTUNE0 VCO Tuning Register bit 0 RW 0 [DEEAR:DEEDR:DEECR] io_cpu.bmp EEPROM_02.xml DEEAR EERPOM Address Register $1E $3E io_cpu.bmp N PA6 EEPROM Page Address bit 6 RW 0 PA5 EEPROM Page Address bit 5 RW 0 PA4 EEPROM Page Address bit 4 RW 0 PA3 EEPROM Page Address bit 3 RW 0 BA2 EEPROM Byte Address bit 2 RW 0 BA1 EEPROM Byte Address bit 1 RW 0 BA0 EEPROM Byte Address bit 0 RW 0 DEEDR EEPROM Data Register $1D $3D io_cpu.bmp N ED7 EEPROM Data Register bit 7 RW 0 ED6 EEPROM Data Register bit 6 RW 0 ED5 EEPROM Data Register bit 5 RW 0 ED4 EEPROM Data Register bit 4 RW 0 ED3 EEPROM Data Register bit 3 RW 0 ED2 EEPROM Data Register bit 2 RW 0 ED1 EEPROM Data Register bit 1 RW 0 ED0 EEPROM Data Register bit 0 RW 0 DEECR EEPROM Control Register $1C $3C io_flag.bmp Y BSY EERPOM Busy Bit R 0 EEU EEPROM Unlock Bit RW 0 EEL EEPROM Load Bit RW 0 EER EEPROM Read Bit RW 0 [WDTCR] io_watch.bmp WDTCR Watchdog Timer Control Register $22 $42 io_flag.bmp Y WDTOE WDDE RW This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure. RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW WDOG_TIMER_PRESCALE_3BITS 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [BTCNT:BTCR] io_timer.bmp 29569 BTCNT Timer Count register $20 $40 io_timer.bmp N C7 Timer Count Register bit 7 RW 0 C6 Timer Count Register bit 7 RW 0 C5 Timer Count Register bit 7 RW 0 C4 Timer Count Register bit 7 RW 0 C3 Timer Count Register bit 7 RW 0 C2 Timer Count Register bit 7 RW 0 C1 Timer Count Register bit 7 RW 0 C0 Timer Count Register bit 7 RW 0 BTCR Bit Timer Counter Control Register $21 $41 io_timer.bmp Y C9 Timer Count Register bit 9 RW 0 C8 Timer Count Register bit 8 RW 0 M1 Bit Timer Mode bit 1 RW 0 M0 Bit Timer Mode bit 0 RW 0 IE Interrupt Enable RW 0 F2 Flag 2 RW 0 DATA Data Bit RW 0 F0 Flag 0 RW 0 [IO_ENAB:IO_DATOUT:IO_DATIN] io_port.bmp AVRSimIOPort.SimIOPort IO_ENAB I/O Enable Register $30 $50 io_port.bmp N IOE5 I/O Enable bit 5 RW 0 IOE4 I/O Enable bit 4 RW 0 IOE3 I/O Enable bit 3 RW 0 IOE2 I/O Enable bit 2 RW 0 IOE1 I/O Enable bit 1 RW 0 IOE0 I/O Enable bit 0 RW 0 IO_DATOUT I/O Data Out Register $31 $51 io_port.bmp N IOO5 I/O Data Out Register bit 5 RW 0 IOO4 I/O Data Out Register bit 4 RW 0 IOO3 I/O Data Out Register bit 3 RW 0 IOO2 I/O Data Out Register bit 2 RW 0 IOO1 I/O Data Out Register bit 1 RW 0 IOO0 I/O Data Out Register bit 0 RW 0 IO_DATIN I/O Data In register $32 $52 io_port.bmp N IOI5 I/O Data In Register bit 5 R IOI4 I/O Data In Register bit 4 R IOI3 I/O Data In Register bit 3 R IOI2 I/O Data In Register bit 2 R IOI1 I/O Data In Register bit 1 R IOI0 I/O Data In Register bit 0 R [SREG:SPH:SPL:AVR_CONFIG:B_DET:BL_CONFIG] [SPH:SPL] io_cpu.bmp SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R $3E $5E io_sph.bmp N SP10 Stack pointer bit 10 RW 0 SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt $3D $5D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 AVR_CONFIG AVR Configuration Register $33 $53 io_flag.bmp N ACS1 AVR System Clock Select bit 1 RW 0 ACS0 AVR System Clock Select bit 0 RW 0 TM Test Mode RW 0 BD Battery Dead RW 0 BLI Battery Low Indicator RW 0 SLEEP Sleep Bit RW 0 BBM Button Boot Mode RW 0 B_DET Button Detect Register $34 $54 io_sph.bmp N BD5 Button Detect bit 5 RW 0 BD4 Button Detect bit 4 RW 0 BD3 Button Detect bit 3 RW 0 BD2 Button Detect bit 2 RW 0 BD1 Button Detect bit 1 RW 0 BD0 Button Detect bit 0 RW 0 BL_CONFIG Battery Low Configuration Register $35 $55 io_sph.bmp N BL Battery Low RW 0 BLV Battery Low Valid RW 0 BL5 Battery Low Detection Level bit 5 RW 0 BL4 Battery Low Detection Level bit 4 RW 0 BL3 Battery Low Detection Level bit 3 RW 0 BL2 Battery Low Detection Level bit 2 RW 0 BL1 Battery Low Detection Level bit 1 RW 0 BL0 Battery Low Detection Level bit 0 RW 0 [SIMULATOR:STK500:STK500_2:AVRISPmkII] AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0 0x00 0x00 0x00 0x00 0xD0 0 0 0 0x00 0x00 0x00 0 200 100 25 32 0 3 0x53 1 1 45 1 0x02 32 10 0x40 0x00 0x20 0x00 0x00 0x02 4 6 0xC0 0x00 0xA0 0x00 0xFF 256 256 4 4 4 4